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HEF40175B_10 PDF预览

HEF40175B_10

更新时间: 2024-11-19 10:44:59
品牌 Logo 应用领域
恩智浦 - NXP 触发器
页数 文件大小 规格书
15页 131K
描述
Quad D-type flip-flop Standardized symmetrical output characteristics

HEF40175B_10 数据手册

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HEF40175B  
Quad D-type flip-flop  
Rev. 6 — 14 December 2010  
Product data sheet  
1. General description  
The HEF40175B is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3),  
a clock input (CP), an overriding asynchronous master reset input (MR), four buffered  
outputs (Q0 to Q3), and four complementary buffered outputs (Q0 to Q3). Information on  
D0 to D3 is transferred to Q0 to Q3 on the LOW-to-HIGH transition of CP if MR is HIGH.  
When LOW, MR resets all flip-flops (Q0 to Q3 = LOW; Q0 to Q3 = HIGH), independent of  
CP and D0 to D3.  
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS  
(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is  
also suitable for use over the full industrial (40 C to +85 C) temperature range.  
2. Features and benefits  
Fully static operation  
5 V, 10 V, and 15 V parametric ratings  
Standardized symmetrical output characteristics  
Operates across the full industrial temperature range from 40 C to +85 C  
Complies with JEDEC standard JESD 13-B  
3. Applications  
Industrial  
Shift registers  
Buffer/storage register  
Pattern generator  
4. Ordering information  
Table 1.  
Ordering information  
All types operate from 40 C to +85 C.  
Type number  
Package  
Name  
Description  
Version  
HEF40175BP  
HEF40175BT  
HEF40175BTT  
DIP16  
SO16  
plastic dual in-line package; 16 leads (300 mil)  
plastic small outline package; 16 leads; body width 3.9 mm  
SOT38-4  
SOT109-1  
SOT403-1  
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm  

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