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HD75161AP PDF预览

HD75161AP

更新时间: 2024-11-29 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 总线收发器线路驱动器或接收器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
12页 245K
描述
Octal General Purpose Interface Bus Transceivers

HD75161AP 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:20Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.24Is Samacsys:N
差分输出:NO驱动器位数:8
输入特性:SCHMITT TRIGGER接口集成电路类型:LINE TRANSCEIVER
接口标准:IEEE-488JESD-30 代码:R-PDIP-T20
JESD-609代码:e0长度:24.5 mm
功能数量:8端子数量:20
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
最大接收延迟:22 ns接收器位数:8
座面最大高度:5.08 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:NO温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED最大传输延迟:20 ns
宽度:7.62 mmBase Number Matches:1

HD75161AP 数据手册

 浏览型号HD75161AP的Datasheet PDF文件第2页浏览型号HD75161AP的Datasheet PDF文件第3页浏览型号HD75161AP的Datasheet PDF文件第4页浏览型号HD75161AP的Datasheet PDF文件第5页浏览型号HD75161AP的Datasheet PDF文件第6页浏览型号HD75161AP的Datasheet PDF文件第7页 
HD75161A  
Octal General Purpose Interface Bus Transceivers  
REJ03D0309–0200Z  
(Previous ADE-205-591 (Z))  
Rev.2.00  
Jul.16.2004  
Description  
The HD75161A is an 8 channel general purpose interface bus transceiver designed to meet the requirements of IEEE  
standard 488-1978. The transceiver is to provide the bus management and data transfer signals during operating in a  
controller instrumentation system. When combined with the HD75160A octal bus transceiver, the HD75161A provides  
the complete 16 wire interface for the IEEE 488 bus. The HD75161A features eight driver receiver pairs connected in a  
front to back configureation to form input/output ports at both the bus and terminal sides. The direction of data through  
these driver receiver pairs is determined by the DC and TE enable signals. The device exhibits a high impedance to the  
bus when VCC = 0 V since the bus terminating resistors are built in. If featurs driver outputs which can handle loads up  
to 48 mA of sink current. Each receiver features p n p transistor inputs for high impedance and guaranteed  
hysteresis of 400 mV for increased noise immunity.  
Features  
Ordering Information  
Part Name  
Package Type  
Packag
n  
Taping Abbreviation  
(Quantity)  
HD75161AP  
DILP-20 pin  
DP
Pin Arrangement  
20 VCC  
19  
18  
17  
16  
15  
14  
REN  
IFC  
NDAC  
5
AV  
EOI  
NRFD  
DAV  
EOI  
6
7
ATN  
SRQ  
GND  
8
13 ATN  
9
12  
11  
SRQ  
DC  
10  
(Top view)  
Rev.2.00, Jul.16.2004, page 1 of 11  

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