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HD74LV1GT86ACME PDF预览

HD74LV1GT86ACME

更新时间: 2024-11-07 05:10:59
品牌 Logo 应用领域
瑞萨 - RENESAS 转换器电平转换器栅极触发器逻辑集成电路石英晶振光电二极管ISM频段
页数 文件大小 规格书
7页 104K
描述
2-input Exclusive-OR Gate / CMOS Logic Level Shifter

HD74LV1GT86ACME 技术参数

生命周期:Active零件包装代码:SOIC
包装说明:TSSOP, TSSOP5/6,.08针数:5
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.48Is Samacsys:N
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G5
JESD-609代码:e6长度:2 mm
负载电容(CL):50 pF逻辑集成电路类型:XOR GATE
最大I(ol):0.006 A功能数量:1
输入次数:2端子数量:5
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP5/6,.08封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:3.3 VProp。Delay @ Nom-Sup:19 ns
传播延迟(tpd):19 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN BISMUTH
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:1.25 mm
Base Number Matches:1

HD74LV1GT86ACME 数据手册

 浏览型号HD74LV1GT86ACME的Datasheet PDF文件第2页浏览型号HD74LV1GT86ACME的Datasheet PDF文件第3页浏览型号HD74LV1GT86ACME的Datasheet PDF文件第4页浏览型号HD74LV1GT86ACME的Datasheet PDF文件第5页浏览型号HD74LV1GT86ACME的Datasheet PDF文件第6页浏览型号HD74LV1GT86ACME的Datasheet PDF文件第7页 
HD74LV1GT86A  
2–input Exclusive–OR Gate / CMOS Logic Level Shifter  
REJ03D0122-1000  
Rev.10.00  
Mar 21, 2008  
Description  
The HD74LV1GT86A performs the Boolean functions Y = A B or Y = AB + AB in positive logic. A common  
application is as a true / complement element. If one of the inputs is low, the other input will be reproduced in true  
form at the output. If one of the inputs is high, the signal on the other input will be reproduced inverted form at the  
output. The input protection circuitry on this device allows over voltage tolerance on the input, allowing the device to  
be used as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V  
CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed operation is suitable for  
the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life.  
Features  
The basic gate function is lined up as Renesas uni logic series.  
Supplied on emboss taping for high-speed automatic mounting.  
TTL compatible input level.  
Supply voltage range : 3.0 to 5.5 V  
Operating temperature range : –40 to +85°C  
Logic-level translate function  
3.0 V CMOS logic 5.0 V CMOS logic (@VCC = 5.0 V)  
1.8 V or 2.5 V CMOS logic 3.3 V CMOS logic (@VCC = 3.3 V)  
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)  
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)  
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)  
All the logical input has hysteresis voltage for the slow transition.  
Ordering Information  
Package Code  
(Previous Code)  
PTSP0005ZC-A  
(CMPAK-5V)  
Package  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
CMPAK–5 pin  
VSON–5 pin  
Abbreviation  
HD74LV1GT86ACME  
HD74LV1GT86AVSE  
CM  
E (3000 pcs/reel)  
E (3000 pcs/reel)  
PUSN0005KA-A  
(TNP-5DV)  
VS  
Note: Please consult the sales office for the above package availability.  
REJ03D0122-1000 Rev.10.00, Mar 21, 2008  
Page 1 of 6  

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