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HD74LS642FPEL PDF预览

HD74LS642FPEL

更新时间: 2024-11-23 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 74K
描述
Octal Bus Transceivers (inverted open-collector outputs)

HD74LS642FPEL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.3
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.4
Is Samacsys:N控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:LS
JESD-30 代码:R-PDSO-G20长度:12.6 mm
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:75 °C
最低工作温度:-20 °C输出特性:OPEN-COLLECTOR
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:25 ns
传播延迟(tpd):25 ns认证状态:Not Qualified
座面最大高度:2.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL EXTENDED
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:5.5 mm
Base Number Matches:1

HD74LS642FPEL 数据手册

 浏览型号HD74LS642FPEL的Datasheet PDF文件第2页浏览型号HD74LS642FPEL的Datasheet PDF文件第3页浏览型号HD74LS642FPEL的Datasheet PDF文件第4页浏览型号HD74LS642FPEL的Datasheet PDF文件第5页浏览型号HD74LS642FPEL的Datasheet PDF文件第6页浏览型号HD74LS642FPEL的Datasheet PDF文件第7页 
HD74LS642  
Octal Bus Transceivers (inverted open-collector outputs)  
REJ03D0490–0200  
Rev.2.00  
Feb.18.2005  
This octal bus transceivers is designed for asynchronous two-way communication between data buses. The devices  
transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction  
control (DIR) input. The enable input (G) can be used to disable the device so that the buses are effectively isolated.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-20 pin  
PRDP0020AC-B  
(DP-20NEV)  
HD74LS642P  
HD74LS642FPEL  
P
PRSP0020DD-B  
(FP-20DAV)  
SOP-20 pin (JEITA)  
FP  
EL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
1A  
VCC  
Enable G  
1B  
3
2A  
4
3A  
2B  
5
4A  
3B  
6
5A  
4B  
7
6A  
5B  
8
7A  
6B  
9
8A  
7B  
10  
GND  
8B  
(Top view)  
Rev.2.00, Feb.18.2005, page 1 of 6  

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