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HD74LS641P PDF预览

HD74LS641P

更新时间: 2024-09-15 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 总线收发器
页数 文件大小 规格书
7页 165K
描述
Octal Bus Transceivers (non-inverted open-collector outputs)

HD74LS641P 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:20
Reach Compliance Code:compliant风险等级:5.4
系列:LSJESD-30 代码:R-PDIP-T20
长度:24.5 mm逻辑集成电路类型:BUS TRANSCEIVER
位数:8功能数量:2
端口数量:2端子数量:20
最高工作温度:75 °C最低工作温度:-20 °C
输出特性:OPEN-COLLECTOR输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):25 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL EXTENDED端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

HD74LS641P 数据手册

 浏览型号HD74LS641P的Datasheet PDF文件第2页浏览型号HD74LS641P的Datasheet PDF文件第3页浏览型号HD74LS641P的Datasheet PDF文件第4页浏览型号HD74LS641P的Datasheet PDF文件第5页浏览型号HD74LS641P的Datasheet PDF文件第6页浏览型号HD74LS641P的Datasheet PDF文件第7页 
HD74LS641  
Octal Bus Transceivers (non-inverted open-collector outputs)  
REJ03D0488–0200  
Rev.2.00  
Feb.18.2005  
This octal bus transceivers is designed for asynchronous two-way communication between data buses. The devices  
transmit data, from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction  
control (DIR) input. The enable input (G) can be used to disable the device so that the buses are effectively isolated.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-20 pin  
PRDP0020AC-B  
(DP-20NEV)  
HD74LS641P  
HD74LS641FPEL  
P
PRSP0020DD-B  
(FP-20DAV)  
SOP-20 pin (JEITA)  
EL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availa
Pin Arrangement  
1
2
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
1A  
VCC  
Enable G  
1B  
2A  
2B  
3B  
4B  
5B  
6B  
9
8A  
7B  
10  
GND  
8B  
(Top view)  
Rev.2.00, Feb.18.2005, page 1 of 6  

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