HD74LS160AFPEL

更新时间： 2024-09-21 05:35:15

品牌	Logo	应用领域
瑞萨 - RENESAS		计数器
页数	文件大小	规格书
11页	204K
描述
Synchronous Decade Counter (direct clear)

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HD74LS160AFPEL 数据手册

HD74LS160A

Synchronous Decade Counter (direct clear)

REJ03D0444–0300

Rev.3.00

Jul.15.2005

This synchronous decade counter features an internal carry look ahead for application in high-speed counting designs.

Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes

coincident with each other when so instructed by the count-enable inputs and internal gating. This mode is operation

eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A

buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This

counter is fully programmable; that is, the output may be preset to either level. As presetting is synchronous, setting up

a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock

pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of this device should be

avoided when the clock is low if the enable inputs are high at or before the transition. The clear function is

asynchronous and a low level at the clear input sets all four of the flip-flop outputs. The carry look-ahead circuitry

provides for cascading counters for n-bit synchronous applications without additional getting. Instrumental in

accomplishing this function is two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T)

must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled

will produced a high-level output pulse with a duration approximately equal to the high-level portion of the Q_Aoutput.

This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low-level

transitions at the enable P or T inputs should occur only when the clock input is high.

Features

•

Ordering Information

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

Part Name

Package Type

DILP-16 pin

PRDP0016AE-B

(DP-16FV)

HD74LS160AP

HD74LS160AFPEL

—

PRSP0016DH-B

(FP-16DAV)

SOP-16 pin (JEITA)

EL (2,000 pcs/reel)

Note: Please consult the sales office for the above package availability.

Pin Arrangement

Clear

V_CC

CLR

Ripple

Carry

Ripple

Carry Output

Clock

Data

Inputs

Outputs

Enable P

GND

Enable T

Load

(Top view)

Rev.3.00, Jul.15.2005, page 1 of 10

12 3 4 5 6 7...11

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与HD74LS160AFPEL相关器件

型号	品牌	获取价格	描述	数据表
HD74LS160AFP-EL	RENESAS	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, FP-16DA
HD74LS160AP	RENESAS	获取价格	Synchronous Decade Counter (direct clear)
HD74LS160AP-E	RENESAS	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16, 6.30 X 19.20 MM, 2
HD74LS160ARP	RENESAS	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, FP-16DN
HD74LS160ARP	HITACHI	获取价格	Decade Counter, LS Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL,
HD74LS160ARP-EL	HITACHI	获取价格	Decade Counter, LS Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL,
HD74LS160P	ETC	获取价格	Synchronous Up Counter
HD74LS161	ETC	获取价格	Synchronous Up Counter
HD74LS161A	RENESAS	获取价格	Synchronous 4-bit Binary Counter (direct clear)
HD74LS161A	HITACHI	获取价格	Synchronous 4-bit Binary Counters(direct clear)

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