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HD74LS157RPEL PDF预览

HD74LS157RPEL

更新时间: 2024-11-08 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 解复用器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 73K
描述
Quadruple 2-line-to-1-line Data Selectors / Multiplexers (noninverted outputs)

HD74LS157RPEL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.17系列:LS
JESD-30 代码:R-PDSO-G16长度:9.9 mm
负载电容(CL):15 pF逻辑集成电路类型:MULTIPLEXER
最大I(ol):0.008 A湿度敏感等级:1
功能数量:4输入次数:2
输出次数:1端子数量:16
最高工作温度:75 °C最低工作温度:-20 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):16 mA
Prop。Delay @ Nom-Sup:14 ns传播延迟(tpd):14 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Multiplexer/Demultiplexers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL EXTENDED端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.95 mm
Base Number Matches:1

HD74LS157RPEL 数据手册

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HD74LS157  
Quadruple 2-line-to-1-line Data Selectors / Multiplexers  
(noninverted outputs)  
REJ03D0442–0200  
Rev.2.00  
Feb.18.2005  
This data selector / multiplexer contains inverters and drivers to supply full on-chip data selection to the four output  
gates. A separate strobe input is provided. A 4-bit word is selected from one of two sources and is routed to the four  
outputs. Then, outputs present true data to minimize propagation delay time.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
PRDP0016AE-B  
(DP-16FV)  
HD74LS157P  
DILP-16 pin  
P
PRSP0016DH-B  
(FP-16DAV)  
HD74LS157FPEL  
HD74LS157RPEL  
SOP-16 pin (JEITA)  
SOP-16 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0016DG-A  
(FP-16DNV)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Select  
1A  
VCC  
S
1A  
1B  
1Y  
G
4A  
4B  
Strobe  
4A  
Inputs  
1B  
Output 1Y  
2A  
Inputs  
4B  
2A  
4Y  
4Y Output  
Inputs  
2B  
2B  
2Y  
3A  
3B  
3A  
Inputs  
3B  
Output 2Y  
GND  
3Y  
3Y Output  
(Top view)  
Rev.2.00, Feb.18.2005, page 1 of 6  

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