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HD74LS156 PDF预览

HD74LS156

更新时间: 2024-09-21 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 解码器解复用器逻辑集成电路驱动
页数 文件大小 规格书
7页 92K
描述
Dual 2-line-to-4-line Decoders / Demultiplexers (with open collector outputs)

HD74LS156 数据手册

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HD74LS156  
Dual 2-line-to-4-line Decoders / Demultiplexers  
(with open collector outputs)  
REJ03D0441–0300  
Rev.3.00  
Jul.13.2005  
This circuit features dual 1-line-to-4-line demultiprexer with individual strobes and common binary-address input.  
When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route  
associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting  
each of the 4-bit sections as desired. Data applied to input 1C is inverted through its outputs. The inverter following  
the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-16 pin  
PRDP0016AE-B  
(DP-16FV)  
HD74LS156P  
HD74LS156RPEL  
P
PRSP0016DG-A  
(FP-16DNV)  
SOP-16 pin (JEDEC)  
FP  
EL (2,500 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Data 1C  
Strobe 1G  
VCC  
Data 2C  
Select Input B  
Strobe 2G  
1G  
1C  
1Y3  
1Y2  
1Y1  
1Y0  
1Y  
1Y  
1Y  
1Y  
3
2
1
0
Select Input A  
2G  
2C  
2Y  
3
2
2Y  
2Y  
2Y  
2Y  
3
2
1
0
Outputs  
2Y  
B
B
B
A
A
B
A
A
Outputs  
2Y  
1
0
2Y  
GND  
(Top view)  
Rev.3.00, Jul.13.2005, page 1 of 6  

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