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HD74HCT74AFP PDF预览

HD74HCT74AFP

更新时间: 2024-11-11 20:10:47
品牌 Logo 应用领域
日立 - HITACHI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
10页 55K
描述
D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, FP-14DA

HD74HCT74AFP 数据手册

 浏览型号HD74HCT74AFP的Datasheet PDF文件第2页浏览型号HD74HCT74AFP的Datasheet PDF文件第3页浏览型号HD74HCT74AFP的Datasheet PDF文件第4页浏览型号HD74HCT74AFP的Datasheet PDF文件第5页浏览型号HD74HCT74AFP的Datasheet PDF文件第6页浏览型号HD74HCT74AFP的Datasheet PDF文件第7页 
HD74HCT74A  
Dual D–type Positive Edge–triggered Flip Flops  
with Clear and Preset  
ADE-205-290 (Z)  
1st. Edition  
June 1999  
Description  
The HD74HCT74A has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin  
package. The logic level present at the data input is transferred to the output during the positive going  
transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level  
at the appropriate input.  
Features  
VCC = 4.5 to 5.5 V operation  
Input terminal has protection diode  
Function Table  
Inputs  
Outputs  
PRE  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
Q
L
H
L
H
X
L
H *1  
H
H *1  
L
L
X
H
H
H
H
H
L
H
L
H
H
L
X
Q0  
Q0  
H : High level  
L : Low level  
X : Immaterial  
: Low to high transition  
Q0 : Level to Q before the indicated steady state input conditions were established.  
Note : 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if  
preset and clear go high simultaneously.  

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