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HD74HCT244 PDF预览

HD74HCT244

更新时间: 2024-11-09 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 驱动器
页数 文件大小 规格书
7页 101K
描述
Octal Buffers/Line Drivers/Line Receivers (with inverted 3-state outputs)

HD74HCT244 数据手册

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HD74HCT244  
Octal Buffers/Line Drivers/Line Receivers  
(with inverted 3-state outputs)  
REJ03D0664–0200  
(Previous ADE-205-553)  
Rev.2.00  
Mar 30, 2006  
Description  
The HD74HCT244 is a non-inverting buffer and has two active low enable (1G and 2G). Each enable independently  
controls 4 buffers.  
This device does not have schmitt trigger inputs.  
Features  
LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility  
High Speed Operation: tpd (A to Y) = 10 ns typ (CL = 50 pF)  
High Output Current: Fanout of 15 LSTTL Loads  
Wide Operating Voltage: VCC = 4.5 to 5.5 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-20 pin  
PRDP0020AC-B  
(DP-20NEV)  
HD74HCT244P  
P
PRSP0020DD-B  
(FP-20DAV)  
HD74HCT244FPEL  
HD74HCT244RPEL  
HD74HCT244TELL  
SOP-20 pin (JEITA)  
SOP-20 pin (JEDEC)  
TSSOP-20 pin  
FP  
RP  
T
EL (2,000 pcs/reel)  
EL (1,000 pcs/reel)  
ELL (2,000 pcs/reel)  
PRSP0020DC-A  
(FP-20DBV)  
PTSP0020JB-A  
(TTP-20DAV)  
Note: Please consult the sales office for the above package availability.  
Function Table  
Inputs  
Output  
G
H
L
A
X
H
L
Y
Z
H
L
L
H : high level  
L
X
Z
:
:
:
low level  
irrelevant  
off (high-impedance) state of a 3-state output  
Rev.2.00 Mar 30, 2006 page 1 of 6  

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