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HD74HC564FPEL-E PDF预览

HD74HC564FPEL-E

更新时间: 2024-01-14 10:15:40
品牌 Logo 应用领域
瑞萨 - RENESAS 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
10页 121K
描述
IC,FLIP-FLOP,OCTAL,D TYPE,HC-CMOS,SOP,20PIN,PLASTIC

HD74HC564FPEL-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:SOP, SOP20,.3Reach Compliance Code:compliant
风险等级:5.84JESD-30 代码:R-PDSO-G20
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:24000000 Hz最大I(ol):0.006 A
功能数量:8端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:2/6 V
认证状态:Not Qualified子类别:FF/Latches
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGEBase Number Matches:1

HD74HC564FPEL-E 数据手册

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HD74HC564, HD74HC574  
Octal D-type Flip-Flops (with 3-state outputs)  
REJ03D0630-0200  
(Previous ADE-205-510)  
Rev.2.00  
Mar 30, 2006  
Description  
These devices are positive edge triggered flip-flops. The difference between HD74HC564 and HD74HC574 is only  
that the former has inverting outputs and the latter has noninvertering outputs.  
Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs on positive  
going transitions of the clock (CK) input. When a high logic level is applied to the output control (OC) input, all  
outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the  
storage elements.  
Features  
High Speed Operation: tpd (Clock to Output) = 13 ns typ (CL = 50 pF)  
High Output Current: Fanout of 15 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-20 pin  
SOP-20 pin (JEITA)  
HD74HC564P  
PRDP0020AC-B  
(DP-20NEV)  
P
HD74HC574P  
HD74HC564FPEL  
HD74HC574FPEL  
PRSP0020DD-B  
(FP-20DAV)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (1,000 pcs/reel)  
PRSP0020DC-A  
(FP-20DBV)  
HD74HC564RPEL SOP-20 pin (JEDEC)  
Note: Please consult the sales office for the above package availability.  
Function Table  
Inputs  
Outputs  
Output Control  
Clock  
Data  
H
HD74HC564  
HD74HC574  
L
L
L
H
H
L
L
L
L
X
Q0  
Z
Q0  
Z
H
X
X
Q0 : level of Q before the indicated Steady-sate input conditions were established.  
Q0 : complement of Q0 or level of Q before the indicated Steady-state input Conditions were established.  
Rev.2.00 Mar 30, 2006 page 1 of 9  

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