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HD74HC563 PDF预览

HD74HC563

更新时间: 2024-11-12 22:55:07
品牌 Logo 应用领域
日立 - HITACHI 锁存器
页数 文件大小 规格书
12页 73K
描述
Octal Transparent Latches (with 3-state outputs)

HD74HC563 数据手册

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HD74HC563/HD74HC573  
Octal Transparent Latches (with 3-state outputs)  
Description  
When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D  
inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at  
the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is  
applied to the output control input, all outputs go to a high impedance state, regardless of what signals are  
present at the other inputs and the state of the storage elements.  
Features  
High Speed Operation: tpd (Data to Q, Q) = 11 ns typ (CL = 50 pF)  
High Output Current: Fanout of 15 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Function Table  
Outputs  
Output Control  
Latch Enable  
Data  
H
HD74HC563  
HD74HD573  
L
L
L
H
H
H
L
L
H
L
L
H
Q0  
Z
X
Q0  
Z
X
X
Q0 :  
Q0 :  
level of Q before the indicated Steady-sate input conditions were established.  
complement of Q0 or level of Q before the indicated Steady-state input conditions were established.  

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