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HD74HC533 PDF预览

HD74HC533

更新时间: 2024-11-12 22:55:07
品牌 Logo 应用领域
日立 - HITACHI 锁存器
页数 文件大小 规格书
11页 69K
描述
Octal D-type Transparent Latches (with 3-state outputs),Octal D-type Transparent Latches (with inverted 3-state outputs)

HD74HC533 数据手册

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HD74HC373/HD74HC533  
Octal D-type Transparent Latches (with 3-state outputs)  
Octal D-type Transparent Latches (with inverted 3-state outputs)  
Description  
When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q  
outputs of HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at  
the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is  
applied to the output control input, all outputs go to a high impedance state, regardless of what signals are  
present at the other inputs and the state of the storage elements.  
Features  
High Speed Operation: tpd (D to Q) = 16 ns typ (CL = 50 pF)  
High Output Current: Fanout of 15 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Function Table  
Output Control  
Enable  
G
HD74HC373  
Q
HD74HC533  
Q
D
H
L
L
L
L
H
H
H
L
H
L
L
H
X
X
No change  
Z
No change  
Z
X
X
Z
:
:
irrelevant  
Off (high-impedance) state of a 3-state output.  

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