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HD74HC51FPEL PDF预览

HD74HC51FPEL

更新时间: 2024-11-27 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS
页数 文件大小 规格书
7页 90K
描述
2-wide 2-input, 2-wide 3-input AND-OR-INVERT Gate

HD74HC51FPEL 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP14,.3针数:14
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:5.19
系列:HC/UHJESD-30 代码:R-PDSO-G14
长度:10.06 mm负载电容(CL):50 pF
逻辑集成电路类型:AND-OR-INVERT GATE最大I(ol):0.004 A
湿度敏感等级:1功能数量:2
输入次数:6端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:28 ns传播延迟(tpd):140 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2.2 mm子类别:Gates
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.5 mmBase Number Matches:1

HD74HC51FPEL 数据手册

 浏览型号HD74HC51FPEL的Datasheet PDF文件第2页浏览型号HD74HC51FPEL的Datasheet PDF文件第3页浏览型号HD74HC51FPEL的Datasheet PDF文件第4页浏览型号HD74HC51FPEL的Datasheet PDF文件第5页浏览型号HD74HC51FPEL的Datasheet PDF文件第6页浏览型号HD74HC51FPEL的Datasheet PDF文件第7页 
HD74HC51  
2-wide 2-input, 2-wide 3-input AND-OR-INVERT Gate  
REJ03D0547-0200  
(Previous ADE-205-419)  
Rev.2.00  
Oct 06, 2005  
Features  
High Speed Operation: tpd = 10.5 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-14 pin  
PRDP0014AB-B  
(DP-14AV)  
HD74HC51P  
P
PRSP0014DF-B  
(FP-14DAV)  
HD74HC51FPEL  
HD74HC51RPEL  
SOP-14 pin (JEITA)  
SOP-14 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0014DE-A  
(FP-14DNV)  
Note: Please consult the sales office for the above package availability.  
Function Table  
1Y = (1A·1B·1C) + (1D·1E·1F)  
Inputs  
Output  
1A  
H
X
L
1B  
H
X
X
X
X
L
1C  
H
X
X
X
X
X
X
X
L
1D  
X
H
L
1E  
X
H
X
L
1F  
X
H
X
X
L
1Y  
L
L
H
H
H
L
L
X
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
L
X
X
L
H
H
H
H
H
L
X
X
L
X
X
X
X
X
L
L
X
X
L
X
H :  
L :  
X :  
High level  
Low level  
Irrelevant  
Rev.2.00, Oct 06, 2005 page 1 of 6  

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