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HD74HC4040RP-EL PDF预览

HD74HC4040RP-EL

更新时间: 2024-11-19 13:08:15
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器
页数 文件大小 规格书
7页 93K
描述
HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16, FP-16DN

HD74HC4040RP-EL 技术参数

生命周期:Contact Manufacturer零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.22Is Samacsys:N
计数方向:UP系列:HC/UH
JESD-30 代码:R-PDSO-G16长度:9.9 mm
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
工作模式:ASYNCHRONOUS位数:12
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
传播延迟(tpd):220 ns认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:NEGATIVE EDGE宽度:3.95 mm
Base Number Matches:1

HD74HC4040RP-EL 数据手册

 浏览型号HD74HC4040RP-EL的Datasheet PDF文件第2页浏览型号HD74HC4040RP-EL的Datasheet PDF文件第3页浏览型号HD74HC4040RP-EL的Datasheet PDF文件第4页浏览型号HD74HC4040RP-EL的Datasheet PDF文件第5页浏览型号HD74HC4040RP-EL的Datasheet PDF文件第6页浏览型号HD74HC4040RP-EL的Datasheet PDF文件第7页 
HD74HC4040  
12-stage Binary Counter  
REJ03D0647-0200  
(Previous ADE-205-534)  
Rev.2.00  
Mar 30, 2006  
Description  
The HD74HC4040 is a 12-stage counter. This device is incremented on the falling edge (negative transition) of the  
input clock, and all its output is reset to a low level by applying a logical high on its reset input.  
Features  
High Speed Operation: tpd (Clock to Q1) = 15 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
HD74HC4040P  
HD74HC4040FPEL  
Package Type  
DILP-16 pin  
SOP-16 pin (JEITA)  
(Previous Code)  
PRDP0016AE-B  
(DP-16FV)  
P
PRSP0016DH-B  
(FP-16DAV)  
FP  
EL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Function Table  
C
Reset  
Outputs State  
L
L
No change  
Advance to next stage  
All outputs are low  
X
H
X: Irrelevant  
Rev.2.00 Mar 30, 2006 page 1 of 6  

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