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HD74HC4040FP-EL PDF预览

HD74HC4040FP-EL

更新时间: 2024-11-19 13:08:15
品牌 Logo 应用领域
日立 - HITACHI 计数器
页数 文件大小 规格书
9页 56K
描述
Binary Counter, HC/UH Series, Asynchronous, Negative Edge Triggered, 12-Bit, Up Direction, CMOS, PDSO16, FP-16DA

HD74HC4040FP-EL 数据手册

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HD74HC4040  
12-stage Binary Counter  
Description  
The HD74HC4040 is a 12-stage counter. This device is incremented on the falling edge (negative  
transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset  
input.  
Features  
High Speed Operation: tpd (Clock to Q1) = 15 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Function Table  
C
Reset  
Outputs State  
L
L
H
No change  
Advance to next stage  
All outputs are low  
X
X: Irrelevant  

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