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HD74HC240RP-EL PDF预览

HD74HC240RP-EL

更新时间: 2024-11-28 13:08:15
品牌 Logo 应用领域
瑞萨 - RENESAS 驱动器
页数 文件大小 规格书
8页 110K
描述
HC/UH SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, SOP-20

HD74HC240RP-EL 技术参数

生命周期:Transferred零件包装代码:SOIC
包装说明:SOP,针数:20
Reach Compliance Code:unknown风险等级:5.06
系列:HC/UHJESD-30 代码:R-PDSO-G20
长度:12.8 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):23 ns认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

HD74HC240RP-EL 数据手册

 浏览型号HD74HC240RP-EL的Datasheet PDF文件第2页浏览型号HD74HC240RP-EL的Datasheet PDF文件第3页浏览型号HD74HC240RP-EL的Datasheet PDF文件第4页浏览型号HD74HC240RP-EL的Datasheet PDF文件第5页浏览型号HD74HC240RP-EL的Datasheet PDF文件第6页浏览型号HD74HC240RP-EL的Datasheet PDF文件第7页 
HD74HC240  
Octal Buffers/Line Drivers/Line Receivers  
(with inverted 3-state outputs)  
REJ03D0594–0200  
(Previous ADE-205-471)  
Rev.2.00  
Jan 31, 2006  
Description  
The HD74HC240 is an inverting buffer and has two active low enables (1G and 2G). Each enable independently  
controls 4 buffers. This device does not have schmitt trigger inputs.  
Features  
High Speed Operation: tpd = 10 ns typ (CL = 50 pF)  
High Output Current: Fanout of 15 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
HD74HC240P  
Package Type  
DILP-20 pin  
PRDP0020AC-B  
(DP-20NEV)  
P
PRSP0020DD-B  
(FP-20DAV)  
HD74HC240FPEL SOP-20 pin (JEITA)  
HD74HC240RPEL SOP-20 pin (JEDEC)  
FP  
RP  
T
EL (2,000 pcs/reel)  
EL (1,000 pcs/reel)  
ELL (2,000 pcs/reel)  
PRSP0020DC-A  
(FP-20DBV)  
PTSP0020JB-A  
(TTP-20DAV)  
HD74HC240TELL  
TSSOP-20 pin  
Note: Please consult the sales office for the above package availability.  
Function Table  
Inputs  
Output  
G
H
L
A
X
H
L
Y
Z
L
L
H
H : high level  
L
X
Z
:
:
:
low level  
irrelevant  
off (high-impedance) state of a 3-state output  
Rev.2.00 Jan 31, 2006 page 1 of 7  

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