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HD74ALVC16835

更新时间： 2024-11-19 05:35:11

品牌	Logo	应用领域
瑞萨 - RENESAS		总线驱动器
页数	文件大小	规格书
12页	3140K
描述
18-bit Universal Bus Driver with 3-state Outputs

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HD74ALVC16835 数据手册

HD74ALVC16835

18-bit Universal Bus Driver with 3-state Outputs

REJ03D0053-0700

(Previous: ADE-205-192E)

Rev.7.00

Apr 07, 2006

Description

The HD74ALVC16835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V_CCoperation.

Data flow from A to Y is controlled by output enable (OE). The device operates in the transparent mode when the latch

enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is

low, the A data is stored in the latch/flip flop on the low to high transition of the CLK. When OE is high, the outputs

are in the high impedance state.

To ensure the high impedance state during power up or power down, OE should be tied to V_CCthrough a pullup

Features

•

Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”

_CC= 2.3 V to 3.6 V

Typical V_OLground bounce < 0.8 V (@V_CC= 3.3 V, Ta = 25°C)

High output current ±24 mA (@V_CC= 3.0 V)

Ordering Information

Package Code

(Previous code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

Part Name

Package Type

HD74ALVC16835TEL TSSOP-56 pin

PTSP0056KA-A

(TTP-56DAV)

EL (1,000 pcs / Reel)

Function Table

Inputs

Output Y

CLK

↑

Y₀

H :

L :

X :

Z :

↑ :

High level

Low level

Immaterial

High impedance

Low to high transition

Notes: 1. Output level before the indicated steady-state input conditions were established, provided that CLK was high

before LE went low.

2. Output level before the indicated steady-state input conditions were established.

Rev.7.00 Apr 07, 2006 page 1 of 11

12 3 4 5 6 7...12

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与HD74ALVC16835相关器件

型号	品牌	获取价格	描述	数据表
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