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HD151BF860

更新时间： 2024-09-18 23:55:07

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HD151BF860 数据手册

HD151BF860

2.5 V PLL Clock Buffer for DDR Application

ADE-205-716 (Z)

Preliminary

Rev.0

Jan. 2003

Description

The HD151BF860 is a high-performance, low-skew, low-jitter, PLL clock buffer. It is specifically

designed for use with DDR (Double Data Rate) PC mother board application.

Features

•

Designed for DDR200/266/333/400 PC mother board clock buffering

Supports 60 MHz to 210 MHz operation range

Distributes one to six differential clock outputs pairs

Spread spectrum clock compatible

External feedback pin (FBIN) is used to synchronize the outputs to the clock input

Supports 2.5 V analog supply voltage (AVDD), and 2.5 V VDD

Ordering Information

Part Name

Package Type

Package Code

Package

Taping

Abbreviation

Abbreviation (Quantity)

HD151BF860TEL

TSSOP-24 pin

TTP-24DBV

EL (1,000 pcs / Reel)

Note: Please consult the sales office for the above package availability.

12 3 4 5 6 7...11

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