HD151012

更新时间： 2024-09-19 05:35:03

品牌	Logo	应用领域
瑞萨 - RENESAS		计数器
页数	文件大小	规格书
14页	218K
描述
8-bit Binary Programmable Counter with Synchronous Preset Enable

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HD151012 数据手册

HD151012

8-bit Binary Programmable Counter with Synchronous Preset

Enable

REJ03D0299–0200Z

(Previous ADE-205-132 (Z))

Preliminary

Rev.2.00

Jul.16.2004

Description

The HD151012 has 8-bit binary down counter and D-type Flip Flop. The counter can set up to max 256 counts and

synchronous preset (SPE) input can preset the data. When the count value is 0, the next clock pulse presets the data to

invert the output. D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the

rise edge. It is applied to generate AC signal for STN type liquid crystal and general-use divider.

Features

•

High speed operation

tpd (CLK or CLK to Q) = 35 ns (typ)

High output current

Fanout of 10 LS TTL Loads

Wide operating voltage

_CC= 2 to 6 V

Low supply current (Ta = 25°C)

_CC(Static) = 4 µA (max)

•

Ordering Information

Part Name

Package Type

Package Code

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD151012TELL

TSSOP-16 pin

TTP-16DAV

ELL (2,000 pcs/reel)

Function Table

Control Inputs

CLR

SPE

Mode

Operation Description

Generally count

Down count at the rise edge of clock (CLK)

Down count at the fall edge of clock (CLK)

Synchronous preset

Jn data is preset at the rise of clock (CLK), the fall of clock

(CLK)

—

Initialize of Q output

Initialize of Q = “L”

Initialize of Q = “H”

Notes: 1. Synchronous preset (SPE) input can set max 256 down counts.

2. When the count value is 0, the next clock pulse presets the data to invert the output.

3. CLR and PR inputs initialize output state.

H : High level

Low level

Immaterial

— : Irrespective of condition

Rev.2.00, Jul.16.2004, page 1 of 13

12 3 4 5 6 7...14

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与HD151012相关器件

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HD151015P	ETC	获取价格	Bus Transceiver
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HD151015T	ETC	获取价格	Bus Transceiver
HD151015TEL	RENESAS	获取价格	9 bit Level Shifter/Transceiver With 3 State Outputs