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HD1-4702/883 PDF预览

HD1-4702/883

更新时间: 2024-11-10 21:53:31
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英特矽尔 - INTERSIL /
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8页 84K
描述
CMOS Programmable Bit Rate Generator

HD1-4702/883 数据手册

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HD-4702/883  
CMOS Programmable Bit Rate Generator  
June 1998  
Features  
Description  
• This Circuit is Processed in Accordance to MIL-STD-883  
and is Fully Conformant Under the Provisions of  
Paragraph 1. 2. 1.  
The HD-4702/883 Bit Rate Generator provides the  
necessary clock signals for digital data transmission sys-  
tems, such as a UART. It generates 13 commonly used bit  
rates using an on-chip crystal oscillator or an external input.  
For conventional operation generating 16 output clock  
pulses per bit period, the input clock frequency must be  
2.4576MHz (i.e., 9600 Baud x 16 x 16, since there is an  
internal ÷ 16 prescaler). A lower input frequency will result in  
a proportionally lower output frequency.  
• HD-4702/883 Provides 13 Commonly Used Bit Rates  
• Uses a 2.4576MHz Crystal/Input for Standard  
Frequency Output (16 Times Bit Rate)  
• Low Power Dissipation  
• Conforms to ElA RS-404  
The HD-4702/883 can provide multi-channel operation with  
a minimum of external logic by having the clock frequency  
• One HD-4702/883 Controls up to Eight Transmission  
Channels  
C
and the ÷ 8 prescaler outputs Q , Q , Q available  
O
0 1 2  
externally. All signals have a 50% duty cycle except 1800  
Baud, which has less than 0.39% distortion.  
• Initialization Circuit Facilitates Diagnostic Fault  
Isolation  
The four rate select inputs (S -S ) select which bit rate is at  
0
3
• On-Chip Input Pull-Up Circuit  
the output (Z). See Truth Table for Rate Select Inputs for  
select code and output bit rate. Two of the 16 select codes  
for the HD-4702/883 do not select an internally generated  
frequency, but select an input into which the user can feed  
either a different frequency, or a static level (High or Low) to  
generate “ZERO BAUD”.  
Ordering Information  
PART  
NUMBER  
TEMPERATURE  
RANGE ( C)  
o
PACKAGE  
PKG. NO.  
F16.3  
HD1-4702/883  
-55 to 125  
CERDIP  
The bit rates most commonly used in modern data terminals  
(110,150, 300,1200, 2400 Baud) require that no more than  
one input be grounded for the HD-4702/883, which is easily  
achieved with a single 5-position switch.  
The HD-4702/883 has an initialization circuit which  
generates a master reset for the scan counter. This signal is  
derived from a digital differentiator that senses the first high  
level on the C input after the E  
input goes low. When  
is high, selecting the crystal input, C must be low. A  
P
CP  
E
CP  
P
high level on C would apply a continuous reset. See Clock  
P
Modes and Initialization below.  
Pinout  
HD-4702/883 (CERDIP)  
TOP VIEW  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Q
Q
Q
V
CC  
0
1
2
I
M
S
S
S
S
Z
0
1
2
3
E
CP  
C
P
O
X
I
X
GND  
C
O
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 2955.2  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
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