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HCS32K/SAMPLE PDF预览

HCS32K/SAMPLE

更新时间: 2024-09-18 14:42:31
品牌 Logo 应用领域
瑞萨 - RENESAS 输入元件逻辑集成电路
页数 文件大小 规格书
11页 285K
描述
HC/UH SERIES, QUAD 2-INPUT OR GATE, CDFP14, ROHS COMPLIANT, CERAMIC, DFP-14

HCS32K/SAMPLE 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.66系列:HC/UH
JESD-30 代码:R-CDFP-F14JESD-609代码:e1
逻辑集成电路类型:OR GATE功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
传播延迟(tpd):22 ns认证状态:Not Qualified
座面最大高度:2.92 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:TIN SILVER COPPER
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL宽度:6.285 mm
Base Number Matches:1

HCS32K/SAMPLE 数据手册

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HCS32MS  
®
Data Sheet  
April 11, 2007  
FN3057.1  
Radiation Hardened Quad 2-Input OR  
Gate  
Features  
• 3 Micron Radiation Hardened SOS CMOS  
Total Dose 200k RAD (Si)  
The Intersil HCS32MS is a Radiation Hardened Quad 2-Input  
OR Gate. A low on both inputs forces the output to a low state.  
2
• SEP Effective LET No Upsets: >100 MEV-cm /mg  
The HCS32MS utilizes advanced CMOS/SOS technology to  
achieve high-speed operation. This device is a member of the  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
-9  
• Single Event Upset (SEU) Immunity < 2 x 10  
Errors/Bit-Day (Typ)  
• Latch-Up Free Under Any Conditions  
• Military Temperature Range: -55°C to +125°C  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
• Input Logic Levels  
The HCS32MS is supplied in a 14 Ld Ceramic flatpack  
(K suffix) or a SBDIP Package (D suffix).  
Ordering Information  
PART  
PART  
TEMP.  
PKG.  
NUMBER  
MARKING  
RANGE (°C)  
PACKAGE DWG. #  
HCS32DMSR Q 5962R95 -55°C to +125°C 14 Ld SBDIP D14.3  
78101VCC  
• V = 30% of V  
IL  
Max  
Min  
CC  
HCS32KMSR Q 5962R95 -55°C to +125°C 14 Ld Ceramic K14.A  
• V = 70% of V  
IH CC  
78101VXC  
Flatpack  
• Input Current Levels I 5µA @ VOL, VOH  
i
HCS32D/  
Sample  
+25°C  
+25°C  
+25°C  
14 Ld SBDIP  
Functional Diagram  
HCS32K/  
Sample  
14 Ld Ceramic  
Flatpack  
An  
(1, 4, 9, 12)  
HCS32HMSR  
Die  
Yn  
Intersil Pb-free hermetic packaged products employ SnAgCu or Au  
termination finish, which are RoHS compliant termination finishes and  
compatible with both SnPb and Pb-free soldering operations. Ceramic  
dual in-line packaged products (CerDIPs) do contain lead (Pb) in the  
seal glass and die attach glass materials. However, lead in the glass  
materials of electronic components are currently exempted per the  
RoHS directive. Therefore, ceramic dual inline packages with Pb-free  
termination finish are considered to be RoHS compliant.  
(3, 6, 8, 11)  
Bn  
(2, 5, 10, 13)  
TABLE 1. TRUTH TABLE  
INPUTS  
OUTPUTS  
An  
L
Bn  
L
Yn  
L
L
H
L
H
H
H
H
H
H
NOTE: L = Logic Level Low, H = Logic level High  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 1995, 2007. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  

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