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HCPL-2601W PDF预览

HCPL-2601W

更新时间: 2024-11-05 00:01:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电输出元件
页数 文件大小 规格书
12页 584K
描述
HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS

HCPL-2601W 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.67Is Samacsys:N
其他特性:UL RECOGNIZED配置:SINGLE
标称数据速率:10 MBps最大正向电流:0.05 A
最大绝缘电压:2500 V安装特点:THROUGH HOLE MOUNT
元件数量:1最大通态电流:0.05 A
最高工作温度:85 °C最低工作温度:-40 °C
光电设备类型:LOGIC IC OUTPUT OPTOCOUPLER最大功率耗散:0.085 W
标称响应时间:7.5e-8 ns子类别:Optocoupler - IC Outputs
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:NOBase Number Matches:1

HCPL-2601W 数据手册

 浏览型号HCPL-2601W的Datasheet PDF文件第2页浏览型号HCPL-2601W的Datasheet PDF文件第3页浏览型号HCPL-2601W的Datasheet PDF文件第4页浏览型号HCPL-2601W的Datasheet PDF文件第5页浏览型号HCPL-2601W的Datasheet PDF文件第6页浏览型号HCPL-2601W的Datasheet PDF文件第7页 
July 2005  
Single-channel: 6N137, HCPL-2601, HCPL-2611  
Dual-Channel: HCPL-2630, HCPL-2631  
High Speed-10 MBit/s Logic Gate Optocouplers  
Features  
Description  
Very high speed-10 MBit/s  
Superior CMR-10 kV/µs  
Double working voltage-480V  
Fan-out of 8 over -40°C to +85°C  
Logic gate output  
Strobable output  
Wired OR-open collector  
U.L. recognized (File # E90700)  
The 6N137, HCPL-2601/2611 single-channel and HCPL-2630/  
2631 dual-channel optocouplers consist of a 850 nm AlGaAS  
LED, optically coupled to a very high speed integrated photo-  
detector logic gate with a strobable output. This output features  
an open collector, thereby permitting wired OR outputs. The  
coupled parameters are guaranteed over the temperature range  
of -40°C to +85°C. A maximum input signal of 5 mA will provide  
a minimum output sink current of 13mA (fan out of 8).  
An internal noise shield provides superior common mode rejec-  
tion of typically 10kV/µs. The HCPL- 2601 and HCPL- 2631 has  
a minimum CMR of 5 kV/µs. The HCPL-2611 has a minimum  
CMR of 10 kV/µs.  
Applications  
Ground loop elimination  
LSTTL to TTL, LSTTL or 5-volt CMOS  
Line receiver, data transmission  
Data multiplexing  
Switching power supplies  
Pulse transformer replacement  
Computer-peripheral interface  
Package  
Schematic  
VCC  
N/C  
1
8
VCC  
+
1
8
8
VF1  
_
VE  
+
2
3
7
6
5
V01  
2
3
7
6
5
1
VF  
_
_
VO  
V02  
VF2  
GND  
N/C  
4
GND  
+
4
8
8
6N137  
HCPL-2601  
HCPL-2611  
HCPL-2630  
HCPL-2631  
1
1
Truth Table (Positive Logic)  
Input  
Enable  
Output  
H
H
L
H
H
H
L
L
H
H
L
L
L
H
L
NC  
NC  
H
A 0.1µF bypass capacitor must be connected between pins 8 and 5. (See note 1)  
©2005 Fairchild Semiconductor Corporation  
1
www.fairchildsemi.com  
Single-channel: 6N137, HCPL-2601, HCPL-2611 Dual-Channel: HCPL-2630, HCPL-2631 Rev. 1.0.3  

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