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HCPL-2601 PDF预览

HCPL-2601

更新时间: 2024-11-04 00:01:35
品牌 Logo 应用领域
QT 光电输出元件
页数 文件大小 规格书
11页 179K
描述
HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS

HCPL-2601 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:0.300 INCH, DIP-8Reach Compliance Code:unknown
风险等级:5.7其他特性:UL RECOGNIZED
配置:SINGLE标称数据速率:10 MBps
最大正向电流:0.05 A最大绝缘电压:2500 V
JESD-609代码:e0元件数量:1
最大通态电流:0.05 A最高工作温度:85 °C
最低工作温度:-40 °C光电设备类型:LOGIC IC OUTPUT OPTOCOUPLER
最小供电电压:4.5 V端子面层:Tin/Lead (Sn/Pb)
Base Number Matches:1

HCPL-2601 数据手册

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HIGH SPEED-10 MBit/s  
LOGIC GATE OPTOCOUPLERS  
SINGLE-CHANNEL  
6N137  
DUAL-CHANNEL  
HCPL-2630  
HCPL-2601  
HCPL-2611  
HCPL-2631  
DESCRIPTION  
The 6N137, HCPL-2601/2611 single-channel and HCPL-2630/2631 dual-channel  
optocouplers consist of a 850 nm AlGaAS LED, optically coupled to a very high  
speed integrated photodetector logic gate with a strobable output. This output  
features an open collector, thereby permitting wired OR outputs. The coupled  
parameters are guaranteed over the temperature range of -40°C to +85°C. A  
maximum input signal of 5 mA will provide a minimum output sink current of 13  
mA (fan out of 8).  
8
1
An internal noise shield provides superior common mode rejection of typically 10  
kV/µs. The HCPL- 2601 and HCPL- 2631 has a minimum CMR of 5 kV/µs.  
The HCPL-2611 has a minimum CMR of 10 kV/µs.  
8
8
1
1
FEATURES  
• Very high speed-10 MBit/s  
• Superior CMR-10 kV/µs  
• Double working voltage-480V  
• Fan-out of 8 over -40°C to +85°C  
• Logic gate output  
• Strobable output  
• Wired OR-open collector  
• U.L. recognized (File # E90700)  
VCC  
N/C  
+
1
8
VCC  
+
1
8
VF1  
_
VE  
2
3
7
6
5
V01  
2
3
7
6
5
VF  
_
_
VO  
V02  
VF2  
GND  
N/C  
4
GND  
+
4
APPLICATIONS  
• Ground loop elimination  
• LSTTL to TTL, LSTTL or 5-volt CMOS  
• Line receiver, data transmission  
• Data multiplexing  
Single-channel  
circuit drawing  
Dual-channel  
circuit drawing  
• Switching power supplies  
• Pulse transformer replacement  
• Computer-peripheral interface  
TRUTH TABLE  
(Positive Logic)  
Input  
Enable  
Output  
H
L
H
H
L
H
H
H
L
H
L
L
L
H
L
NC  
NC  
H
µF bypass capacitor must be connected between pins 8 and 5.  
A 0.1  
(See note 1)  
8/10/99  
200002A  

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