Very High CMR, Wide V Logic
CC
Gate Optocouplers
HCPL-2201 HCPL-2202
HCPL-2211 HCPL-2212
HCPL-2231 HCPL-2232
HCPL-0201 HCPL-0211
HCNW2201 HCNW2211
Technical Data
Features
• MIL-STD-1772 Version
Available
(HCPL-52XX/62XX)
Description
• 10 kV/µs Minimum Common
Mode Rejection (CMR) at
VCM = 1000 V
The HCPL-22XX, HCPL-02XX,
and HCNW22XX are optically-
coupled logic gates. The
(HCPL-2211/2212/0211/
2232, HCNW2211)
• Wide Operating VCC Range:
4.5 to 20 Volts
• 300 ns Propagation Delay
Guaranteed over the Full
Temperature Range
• 5 Mbd Typical Signal Rate
• Low Input Current (1.6 mA
to 1.8 mA)
Applications
• Isolation of High Speed
Logic Systems
• Computer-Peripheral
Interfaces
• Microprocessor System
Interfaces
• Ground Loop Elimination
• Pulse Transformer
Replacement
HCPL-22XX, and HCPL-02XX
contain a GaAsP LED while the
HCNW22XX contains an AlGaAs
LED. The detectors have totem
pole output stages and optical
receiver input stages with built-in
Schmitt triggers to provide logic-
compatible waveforms, eliminat-
ing the need for additional
waveshaping.
• Hysteresis
• Totem Pole Output (No
Pullup Resistor Required)
• High Speed Line Receiver
• Power Control Systems
A superior internal shield on the
HCPL-2211/12, HCPL-0211,
• Available in 8-Pin DIP,
SOIC-8, Widebody Packages
• Guaranteed Performance
from -40°C to 85°C
Functional Diagram
HCPL-2201/11
HCPL-0201/11
HCNW2201/11
HCPL-2202/12
NC
ANODE
CATHODE
NC
1
2
3
4
8
7
6
5
NC
ANODE
CATHODE
NC
1
2
3
4
8
7
6
5
V
V
V
CC
CC
• Safety Approval
UL Recognized -2500 V rms
for 1 minute (5000 V rms
for 1 minute for
HCNW22XX) per UL1577
CSA Approved
NC
O
NC
V
O
GND
GND
SHIELD
SHIELD
VDE 0884 Approved with
HCPL-2231/32
VIORM = 630 V peak (HCPL-
2211/2212 Option 060 only)
and VIORM = 1414 V peak
(HCNW22XX only)
BSI Certified (HCNW22XX
only)
ANODE 1
CATHODE 1
CATHODE 2
ANODE 2
1
2
3
4
8
7
6
5
V
V
CC
TRUTH TABLE
(POSITIVE LOGIC)
LED
V
O
O1
ON
OFF
HIGH
LOW
V
O2
GND
SHIELD
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component
to prevent damage and/or degradation which may be induced by ESD.