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HCPL-0723-500 PDF预览

HCPL-0723-500

更新时间: 2024-09-25 12:46:23
品牌 Logo 应用领域
惠普 - HP 光电输出元件
页数 文件大小 规格书
12页 252K
描述
50 MBd 2 ns PWD High Speed CMOS Optocoupler

HCPL-0723-500 数据手册

 浏览型号HCPL-0723-500的Datasheet PDF文件第2页浏览型号HCPL-0723-500的Datasheet PDF文件第3页浏览型号HCPL-0723-500的Datasheet PDF文件第4页浏览型号HCPL-0723-500的Datasheet PDF文件第5页浏览型号HCPL-0723-500的Datasheet PDF文件第6页浏览型号HCPL-0723-500的Datasheet PDF文件第7页 
Agilent HCPL-7723 & HCPL-0723  
50 MBd 2 ns PWD  
High Speed CMOS Optocoupler  
Data Sheet  
Features  
• +5 V CMOS compatibility  
• High speed: 50 MBd min.  
• 2 ns max. pulse width distortion  
• 22 ns max. prop. delay  
Description  
Basic building blocks of HCPL-  
7723/0723 are a CMOS LED  
driver IC, a high speed LED and a  
CMOS detector IC. A CMOS logic  
input signal controls the LED  
driver IC, which supplies current  
to the LED. The detector IC  
incorporates an integrated  
photodiode, a high speed  
Available in either 8-pin DIP or  
SO-8 package style respectively, the  
HCPL-7723 or HCPL-0723  
optocoupler utilize the latest CMOS  
IC technology to achieve out-  
standing speed performance of  
minimum 50 MBd data rate and  
2 ns maximum pulse width  
distortion.  
• 16 ns max. prop. delay skew  
• 10 kV/µs min. common mode  
rejection  
• –40 to 85°C temperature range  
• Safety and regulatory approvals  
(Pending)  
UL recognized  
– 2500 V rms for 1 min. per UL1577  
for HCPL-7723  
– 3750 V rms for 1 min. per UL1577  
for HCPL-0723  
transimpedance amplifier, and a  
voltage comparator with an  
output driver.  
CSA component acceptance  
notice #5  
Functional Diagram  
VDE 0884  
– Viorm = 630 Vpeak for HCPL-7723  
option 060  
– Viorm = 560 Vpeak for HCPL-0723  
option 060  
**V  
1
2
8
7
V
**  
DD2  
DD1  
V
NC*  
I
I
O
3
4
6
5
*
V
O
Applications  
LED1  
• Digital fieldbus isolation: CC-Link,  
DeviceNet, Profibus, SDS  
GND  
GND  
2
1
SHIELD  
Isolated A/D or D/A conversion  
*
PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT  
UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE.  
PIN 7 IS NOT CONNECTED INTERNALLY.  
• Multiplexed data transmission  
• High Speed Digital Input/Output  
• Computer peripheral interface  
• Microprocessor system interface  
** A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN  
PINS 1 AND 4, AND 5 AND 8.  
TRUTH TABLE  
(POSITIVE LOGIC)  
V , INPUT  
I
LED1  
V
, OUTPUT  
O
H
L
OFF  
ON  
H
L
CAUTION: It is advised that normal static precautions be taken in handling and assembly of  
this component to prevent damage and/or degradation, which may be induced by ESD.  

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