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HCGD16584EF

更新时间： 2024-09-17 19:38:11
品牌 Logo 应用领域
英特尔 - INTEL ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
15页 174K
描述
Receiver, 1-Func, Bipolar, CBGA132, 13 X 13 MM, CERAMIC, BGA-132

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中文翻译

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HCGD16584EF 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：BGA,针数：132
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.82JESD-30 代码：S-CBGA-B132
长度：13 mm负电源额定电压：-5.2 V
功能数量：1端子数量：132
最高工作温度：70 °C最低工作温度：
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
认证状态：Not Qualified座面最大高度：2.1 mm
标称供电电压：3.3 V表面贴装：YES
技术：BIPOLAR电信集成电路类型：ATM/SONET/SDH RECEIVER
温度等级：COMMERCIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
宽度：13 mmBase Number Matches：1

HCGD16584EF 数据手册

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10 Gbit/s  
Receiver, CDR and  
DeMUX  
GD16584/GD16588  
(FEC)  
an Intel company  
Preliminary  
General Description  
Features  
l
GD16584 and GD16588 are Receiver  
chips for use in STM-64/192 and Optical  
Transport Networking (OTN) systems.  
500 ppm from the reference clock, it  
automatically switches the phase and fre-  
quency detector into the PLL loop. In the  
auto lock mode the locking range is  
selectable between 500 or 2000 ppm.  
Complete Clock and Data Recovery  
IC with auto acquisition.  
l
1:16 DeMUX with differential  
622 Mbit/s data outputs  
The component is available in two ver-  
sions:  
l
u
GD16584 for 9.5328 Gbit/s.  
GD16588 for 10.66 Gbit/s for OTN or  
When the VCO frequency is within the  
lock range, the Bang-Bang Phase Detec-  
tor takes over. It controls the phase of  
the VCO until the sampling point of data  
is in the middle of the bit period, where  
the eye opening is largest. A ±40 mV  
Decision Threshold Control (DTC) is pro-  
vided at the 10 Gbit/s input.  
622 MHz Clock output.  
u
l
Forward Error Correction (FEC).  
Except the different operating bit rates  
the two versions are functional identical.  
LVDS compatible clock and data  
outputs.  
l
OIF99.102.5 compliant timing.  
The receiver is a Clock and Data Reco-  
very IC with:  
l
155 or 622 MHz Reference Clock.  
u
a low noise VCO  
a Bang-Bang Phase Detector  
l
u
The 10 Gbit/s input data is sampled and  
de-multiplexed by the 1:16 DeMUX. The  
parallel output interface is synchronised  
with the 622 MHz output clock. The clock  
and data outputs are LVDS compatible.  
Input Decision Threshold Control  
(DTC): ±40 mV.  
u
a 1:16 De-multiplexer  
a Lock Detect  
a Phase and Frequency Detector.  
u
l
u
Low noise VCO with 5 % tuning  
range.  
Clock and data are regenerated by using  
a Phase Locked Loop (PLL) with an ex-  
ternal passive loop filter.  
l
The device operates from a dual -5.2 V  
and +3.3 V power supply. The power dis-  
sipation is 3.3 W, typical.  
Dual supply operation: -5.2 V and  
+3.3 V.  
The VCO frequency is controlled by one  
of the two Phase Detectors in order to  
ensure capture and lock to the line data  
rate. The Lock Detector circuit monitors  
the VCO frequency and determines when  
the VCO is within the lock range. When  
the frequency deviates more than  
l
Power dissipation: 3.3 W (typ).  
The device is manufactured in a Silicon  
Bipolar process and packaged in an 132  
ball 13 × 13 mm Ceramic/Plastic Ball  
Grid Array (BGA).  
l
Silicon Bipolar technology.  
l
Available in three package versions:  
–
–
–
EB: 132 ball (16 mill) Ceramic  
BGA 13 × 13 mm  
EF: 132 ball (20 mill) Ceramic  
BGA 13 × 13 mm  
FB: 132 ball (20 mill) Plastic  
BGA 13 × 13 mm  
VCO  
CKOUT  
CKOUTN  
Timing Control  
VCTL  
DO0  
DON0  
l
Available in two versions:  
Parallel  
Output  
Data  
1:16  
–
–
GD16584 for 10 Gbit/s  
GD16588 for 10.66 Gbit/s  
DI  
DIN  
Bang  
Bang  
Demultiplexer  
Phase  
Detector  
DO15  
DON15  
Decision  
Threshold  
Control  
DTC  
DTCN  
Applications  
U
D
PCTL  
Phase  
Frequency  
Detector  
l
Telecommunication systems:  
–
–
–
SDH STM-64  
(PHIGH)  
(PLOW)  
REFCK  
REFCKN  
SONET OC-192.  
Optical Transport Networking  
(OTN)  
1/4  
Lock  
–
FEC applications  
Detect  
LOCK  
l
l
Fibre optic test equipment.  
Submarine systems.  
RESET TCK  
SEL3  
SEL1  
SEL2  
VCC  
VDD  
VDDA VDDO  
VEE  
VEEA  
Data Sheet Rev.: 12  
1234567...15

中文翻译

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