Datasheet > HCF4724

HCF4724

更新时间： 2024-11-18 23:54:59

品牌	Logo	应用领域
其他 - ETC		双倍数据速率
页数	文件大小	规格书
14页	781K
描述
8 BIT ADDRESSABLE LATCH

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中文翻译

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数据手册

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HCF4724 数据手册

HCF4724B

8 BIT ADDRESSABLE LATCH

■

SERIAL DATA INPUT - ACTIVE PARALLEL

OUTPUT

STORAGE REGISTER CAPABILITY -

MASTER CLEAR

■

CAN FUNCTION AS DEMULTIPLEXER

QUIESCENT CURRENT SPECIFIED UP TO

20V

DIP

SOP

■

STANDARDIZED SYMMETRICAL OUTPUT

CHARACTERISTICS

INPUT LEAKAGE CURRENT

ORDER CODES

PACKAGE

I = 100nA (MAX) AT V = 18V T = 25°C

TUBE

T & R

■

100% TESTED FOR QUIESCENT CURRENT

MEETS ALL REQUIREMENTS OF JEDEC

JESD13B "STANDARD SPECIFICATIONS

FOR DESCRIPTION OF B SERIES CMOS

DEVICES"

DIP

HCF4724BEY

HCF4724BM1

SOP

HCF4724M013TR

WRITE DISABLE is high, data entry is inhibited;

however, all 8 outputs can be continuously read

independent of WRITE DISABLE and address

inputs. A master RESET input is available, which

resets all bits to a logic "0" level when RESET and

WRITE DISABLE are at a high level. When

RESET is at a high level, and WRITE DISABLE is

at a low level, the latch acts as a 1-of-8

demultiplexer; the bit that is addressed has an

active output which follows the data input, while all

unaddressed bits are held to a logic "0" level.

DESCRIPTION

HCF4724B is a monolithic integrated circuit

fabricated in Metal Oxide Semiconductor

technology available in DIP and SOP packages.

HCF4724B, an 8-bit addressable latch, is a

serial-input, parallel output storage register that

can perform a variety of functions. Data is input to

a particular bit in the latch when the bit is

addressed (by means of input A0, A1, A2) and

when WRITE DISABLE is at a low level. When

PIN CONNECTION

October 2002

1/14

12 3 4 5 6 7...14

中文翻译

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