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HCF4085BC1 PDF预览

HCF4085BC1

更新时间: 2024-11-19 22:17:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路输入元件
页数 文件大小 规格书
13页 300K
描述
DUAL 2-WIDE 2-INPUT AND-OR-INVERTER GATE

HCF4085BC1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:PLASTIC, LCC-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.78Is Samacsys:N
其他特性:EXPANDABLE系列:4000/14000/40000
JESD-30 代码:S-PQCC-J20JESD-609代码:e3
长度:8.965 mm负载电容(CL):50 pF
逻辑集成电路类型:AND-OR-INVERT GATE功能数量:2
输入次数:4端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/15 VProp。Delay @ Nom-Sup:620 ns
传播延迟(tpd):450 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:4.57 mm
子类别:Gates最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.965 mmBase Number Matches:1

HCF4085BC1 数据手册

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HCC/HCF4085B  
DUAL 2-WIDE 2-INPUT AND-OR-INVERTER GATE  
.
MEDIUM-SPEED OPERATION – tPHL = 90ns ;  
tPLH = 125ns (TYP.) AT 10V  
INDIVIDUAL INHIBIT CONTROLS  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
5V, 10V, AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF 100nA AT 18V AND  
25°C FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVE STANDARD N°. 13A, ”STANDARD  
SPECIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
.
.
.
EY  
F
.
(Ceramic Frit Seal Package)  
(Plastic Package)  
.
.
.
M1  
C1  
(Micro Package)  
(Plastic Chip Carrier)  
ORDER CODES :  
HCC4085BF  
HCF4085BM1  
HCF4085BEY  
HCF4085BC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC4085B (extended temperature range) and  
HCF4085B (intermediate temperature range) are  
monolithic integrated circuit, available in 14-lead  
dual in-line plastic or ceramic package and plastic  
micropackage.  
The HCC/HCF4085B contains a pair of AND-OR-  
INVERT gates, each consisting of two 2-input AND  
gates driving a 3-input NOR gate. Individual inhibit  
controls are provided for both A-O-I gates.  
September 1988  
1/13  

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