Datasheet > GVT81128P36T-10

GVT81128P36T-10

更新时间： 2024-11-20 08:47:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
14页	61K
描述
Standard SRAM, 128KX36, 5ns, CMOS, PQFP176, TQFP-176

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GVT81128P36T-10 数据手册

ADVANCE INFORMATION

GVT81256P36/GVT81128P36

256K/128K X 36 PIPELINED SRAM

GALVANTECH, INC.

DUAL I/O

DUAL ADDRESS

SYNCHRONOUS SRAM

256K/128K X 36 SRAM

+3.3V SUPPLY, FULLY REGISTERED

TWO BI-DIRECTIONAL DATA BUSES

FEATURES

GENERAL DESCRIPTION

•

Fast clock speed: 133, 100, and 83 MHz

Fast Access Times: 4.0/5.0/6.0 ns Max

Single Clock Operation

Single 3.3V -5% and +5% power supply VCC

Separate VCCQ for output buffer

Two chip enables for simple depth expansion

Address, Data Input, CE1X#, CE2X, CE1Y#, CE2Y,

PTX#, PTY#, WEX#, WEY#, and Data Output Registers

On-Chip

The GVT81256P36/GVT81128P36 SRAM integrates

262,144x36/131,072x36 SRAM cells with advanced

synchronous peripheral circuitry. It employs high-speed, low

power CMOS designs using advanced triple-layer polysilicon,

double-layer metal technology. Each memory cell consists of

four transistors and two high valued resistors.

The GVT81256P36/GVT81128P36 allows the user to

concurrently perform reads, writes, or pass-through cycles in

combination on the two data ports. The two address ports

(AX, AY) determine the read or write locations for their

respective data ports (DQX, DQY).

All input pins except output enable pins (OEX#, OEY#)

are gated by registers controlled by a positive-edge-triggered

clock input (CLK). The synchronous inputs include all

addresses, all data inputs, depth-expansion chip enables

(CE1X#, CE2X, CE1Y# and CE2Y), pass-through controls

(PTX# and PTY#), and read-write control (WEX# and

WEY#).

•

Concurrent Reads and Writes

Two Bi-Directional Data Buses

Can be Configured as Separate I/O

Pass-Through Feature

Asynchronous Output Enables (OEX#, OEY#)

LVTTL Compatible I/O

Self-Timed Write

Automatic power down

176-Pin TQFP Package

The pass-through feature allows data to be passed from

one port to the other, in either direction. The PTX# input must

be asserted to pass data from port X to port Y. The PTY# will

likewise pass data from port Y to port X. A pass-through

operation takes precedence over a read operation.

For the case when AX and AY are the same, certain

protocols are followed. If both ports are read, the reads occur

normally. If one port is written and the other is read, the read

from the array will occur before the data is written. If both

ports are written, only the data on DQY will be written to the

array.

OPTIONS

MARKING

•

Timing

4.0ns access/7.5ns cycle

5.0ns access/10.0 cycle

6.0ns access/12.0 cycle

-7.5

-10

-12

•

Packages

176-pin TQFP

The GVT81256P36/GVT81128P36 operate from a +3.3V

power supply. All inputs and outputs are LVTTL compatible.

These dual I/O, dual address synchronous SRAMs are well

suited for ATM, Ethernet switches, routers, cell/frame buffers,

SNA switches and shared memory applications.

Galvantech, Inc. reserves the right to chang e

products or specifications without notice.

Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051

Tel (408) 566-0688 Fax (408) 566-0699 Web Site www.galvantech.com

Rev. 12/99

12 3 4 5 6 7...14

中文翻译

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与GVT81128P36T-10相关器件

型号	品牌	获取价格	描述	数据表
GVT81128P36T-12	CYPRESS	获取价格	Standard SRAM, 128KX36, 6ns, CMOS, PQFP176, TQFP-176
GVT81128P36T-7.5	CYPRESS	获取价格	Standard SRAM, 128KX36, 4ns, CMOS, PQFP176, TQFP-176
GVT81256K36T-10	CYPRESS	获取价格	Multi-Port SRAM, 256KX36, 5ns, CMOS, PQFP176, TQFP-176
GVT81256K36T-12	CYPRESS	获取价格	Multi-Port SRAM, 256KX36, 6ns, CMOS, PQFP176, TQFP-176
GVT81256P36T-10	CYPRESS	获取价格	Standard SRAM, 256KX36, 5ns, CMOS, PQFP176, TQFP-176
GVT81256P36T-12	CYPRESS	获取价格	Standard SRAM, 256KX36, 6ns, CMOS, PQFP176, TQFP-176
GVT81256P36T-7.5	CYPRESS	获取价格	Standard SRAM, 256KX36, 4ns, CMOS, PQFP176, TQFP-176
GVX040A0X4-SR-P-HZ	LINEAGEPOWER	获取价格	40A Analog Mega DLynxTM:
GVX0-54/B12.000MHZ	GOLLEDGE	获取价格	LVPECL Output Clock Oscillator, 12MHz Nom
GVX0-54/B155.520MHZ	GOLLEDGE	获取价格	暂无描述

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