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GVT7164B19C-10 PDF预览

GVT7164B19C-10

更新时间: 2024-10-30 19:47:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
13页 130K
描述
Standard SRAM, 64KX18, 10ns, CMOS, PQCC52, LCC-52

GVT7164B19C-10 技术参数

生命周期:Active包装说明:QCCJ,
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.8
最长访问时间:10 nsJESD-30 代码:S-PQCC-J52
长度:19.125 mm内存密度:1179648 bit
内存集成电路类型:STANDARD SRAM内存宽度:18
功能数量:1端子数量:52
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX18
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL座面最大高度:4.57 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:19.125 mm
Base Number Matches:1

GVT7164B19C-10 数据手册

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GVT7164B19  
64K X 18 SYNCHRONOUS BURST SRAM  
GALVANTECH, INC.  
64K x 18 SRAM  
SYNCHRONOUS  
BURST SRAM  
+5V SUPPLY WITH CLOCKED,  
REGISTERED INPUTS, BURST COUNTER  
FEATURES  
GENERAL DESCRIPTION  
Fast access times: 8, 9, 10, and 12ns  
Fast clock speed: 83, 66, and 50 MHz  
Provide high performance 2-1-1-1 access rate  
Fast OE# access times: 5 and 6ns  
Single +5V +5% power supply  
3.3V I/O compatible  
Clamp diodes to VSS at all inputs and outputs  
Common data inputs and data outputs  
Byte writeable via dual write enables  
Address, data and control registers  
Internally self-timed WRITE CYCLE  
Automatic power-down for low power applications  
High board density 52-lead PLCC packages  
The Galvantech Synchronous Burst SRAM family  
employs high-speed, low power CMOS designs using  
advanced double-layer polysilicon, double-layer metal  
technology. Each memory cell consists of four transistors and  
two high valued resistors.  
The GVT7164B19 SRAM integrates 65,536 x18 SRAM  
cells with advanced synchronous peripheral circuitry and a 2-  
bit counter for internal burst operation. All synchronous  
inputs are gated by registers controlled by a positive-edge-  
triggered clock input (CLK). The synchronous inputs include  
all addresses, all data inputs, chip enable (CE#), burst control  
inputs (ADSC#, ADSP#, and ADV#), and write enables  
(WEL# and WEH#).  
Asynchronous input includes the output enable (OE#).  
The data outputs (DQ), enabled by OE#, are also  
asynchronous.  
Addresses and chip enables are registered with either  
address status processor (ADSP#) or address status controller  
(ADSC#) input pins. Subsequent burst addresses can be  
internally generated as controlled by the burst advance pin  
(ADV#).  
OPTIONS  
MARKING  
Timing  
8ns access/12ns cycle  
9ns access/15ns cycle  
10ns access/15ns cycle  
12ns access/20ns cycle  
-8  
-9  
-10  
-12  
Packages  
Address, data inputs, and write controls are registered on-  
chip to initiate self-timed WRITE cycle. WRITE cycles can  
be one or two bytes wide as controlled by the write control  
inputs. Individual byte enables allow individual bytes to be  
written. WEL# controls DQ1-DQ8 and DQP1. WEH#  
controls DQ9-DQ16 and DQP2.  
52-pin PLCC  
C
The GVT7164B19 operates from a +5V power supply.  
All inputs and outputs are TTL-compatible. The device is  
TM  
ideally suited for 486, Pentium , 680x0, and for systems that  
are benefited from a wide synchronous data bus.  
Pentium is a trademark of Intel Corporation.  
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051  
Tel (408) 566-0688 Fax (408) 566-0699  
Rev. 12/97  
Galvantech, Inc. reserves the right to change  
products or specifications without notice.  

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