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GVT71128C32T-6 PDF预览

GVT71128C32T-6

更新时间： 2024-10-29 14:50:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
12页 184K
描述
Standard SRAM, 128KX32, 6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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GVT71128C32T-6 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
Is Samacsys：N最长访问时间：6 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：83 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：4194304 bit内存集成电路类型：STANDARD SRAM
内存宽度：32功能数量：1
端子数量：100字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX32输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.002 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.185 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.1 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

GVT71128C32T-6 数据手册

 浏览型号GVT71128C32T-6的Datasheet PDF文件第2页浏览型号GVT71128C32T-6的Datasheet PDF文件第3页浏览型号GVT71128C32T-6的Datasheet PDF文件第4页浏览型号GVT71128C32T-6的Datasheet PDF文件第5页浏览型号GVT71128C32T-6的Datasheet PDF文件第6页浏览型号GVT71128C32T-6的Datasheet PDF文件第7页 
CY7C1340A/  
GVT71128C32  
128K x 32 Synchronous-Pipelined RAM  
The  
CY7C1340A/GVT71128C32  
SRAM  
integrates  
Features  
131,072 × 32 SRAM cells with advanced synchronous  
peripheral circuitry and a two-bit counter for internal burst  
operation. All synchronous inputs are gated by registers  
controlled by a positive-edge-triggered Clock Input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
address-pipelining chip enable (CE), depth-expansion Chip  
Enables (CE2 and CE2), Burst Control Inputs (ADSC, ADSP,  
and ADV), Write Enables (BW1, BW2, BW3, BW4, and BWE),  
and Global Write (GW).  
• Fast access times: 5, 6, and 7 ns  
• Fast clock speed: 100, 83, and 66 MHz  
• Provides high performance 3-1-1-1 access rate  
• Fast OE access times: 5, 6, and 7 ns  
• Optimal for performance (two-cycle chip deselect,  
depth expansion without wait state)  
• Single +3.3V –5% and +10%power supply  
• Supports +2.5V I/O  
• 5V tolerant inputs except I/Os  
• Clamp diodes to VSSQ at all outputs  
• Common data inputs and outputs  
• Byte Write Enable and Global Write control  
• Three chip enables for depth expansion and address  
pipeline  
• Address, control, input, and output pipeline registers  
• Internally self-timed Write Cycle  
• Burst control pins (interleaved or linear burst  
sequence)  
Asynchronous inputs include the Output Enable (OE) and  
Burst Mode Control (MODE). The data outputs (Q), enabled  
by OE, are also asynchronous.  
Addresses and chip enables are registered with either  
Address Status Processor (ADSP) or Address Status  
Controller (ADSC) input pins. Subsequent burst addresses  
can be internally generated as controlled by the Burst Advance  
Pin (ADV).  
Address, data inputs, and Write controls are registered on-chip  
to initiate self-timed Write cycle. Write cycles can be one to  
four bytes wide as controlled by the Write control inputs.  
Individual byte Write allows individual byte to be written. BW1  
controls DQ1–DQ8. BW2 controls DQ9–DQ16. BW3 controls  
DQ17–DQ24. BW4 controls DQ25–DQ32. BW1, BW2, BW3,  
and BW4 can be active only with BWE being LOW. GW being  
LOW causes all bytes to be written. This device also incorpo-  
rates pipelined enable circuit for easy depth expansion without  
penalizing system performance.  
• Automatic power-down for portable applications  
• High-density, high-speed packages  
• Low-capacitive bus loading  
• High 30-pF output drive capability at rated access time  
Functional Description  
The CY7C1340A/GVT71128C32 operates from a +3.3V  
power supply. All inputs and outputs are TTL-compatible. The  
device is ideally suited for 486, Pentium®, 680 × 0, and  
PowerPC™ systems and for systems that benefit from a wide  
synchronous data bus.  
The Cypress Synchronous Burst SRAM family employs  
high-speed, low-power CMOS designs using advanced  
triple-layer polysilicon, double-layer metal technology. Each  
memory cell consists of four transistors and two high valued  
resistors.  
Selection Guide  
7C1340A-100  
7C1340A-83  
71128C36-6  
7C1340A-66  
71128C36-7  
71128C36-5  
Unit  
ns  
Maximum Access Time  
5
225  
2
6
185  
2
7
120  
2
Maximum Operating Current  
Maximum CMOS Standby Current  
mA  
mA  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05153 Rev. *A  
Revised January 16, 2002  
1234567...12

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