Datasheet > GTL2107PW,118

GTL2107PW,118

更新时间： 2025-07-17 19:10:43

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
19页	181K
描述
输出电压类型:Open Drain, Push-Pull;单电路的通道数(channel):12;通道方向类型:Unidirectional;元器件封装:28-TSSOP;

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GTL2107PW,118 数据手册

GTL2107

12-bit GTL−/GTL/GTL+ to LVTTL translator

Rev. 05 — 23 December 2009

Product data sheet

1. General description

The GTL2107 is a customized translator between dual Xeon processors, GTL−/GTL/GTL+

I/O and the Platform Health Management, South Bridge and Power Supply 3.3 V LVTTL

and GTL signals.

2. Features

Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver

Operates at GTL, GTL+ or GTL− levels

EN1 and EN2 enable control

3.0 V to 3.6 V operation

LVTTL I/O not 5 V tolerant

Series termination on the LVTTL outputs of 30 Ω

ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 Class II, Level A which exceeds

500 mA

Package offered: TSSOP28

3. Quick reference data

Table 1.

Quick reference data

T_amb= 25 °C.

Symbol Parameter

V_ref= 0.73 V; V_TT= 1.1 V

Conditions

Min Typ

Max Unit

t_PLH

LOW to HIGH

propagation delay

nA to nBI; see Figure 4

nBI to nA or nAO (open-drain outputs); see Figure 13

nA to nBI; see Figure 4

5.5

t_PHL

HIGH to LOW

propagation delay

nBI to nA or nAO (open-drain outputs); see Figure 13

V_ref= 0.76 V; V_TT= 1.2 V

t_PLH

LOW to HIGH

propagation delay

nA to nBI; see Figure 4

nBI to nA or nAO (open-drain outputs); see Figure 13

nA to nBI; see Figure 4

5.5

t_PHL

HIGH to LOW

propagation delay

nBI to nA or nAO (open-drain outputs); see Figure 13

12 3 4 5 6 7...19

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