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GT2034

更新时间： 2024-11-23 04:19:55
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德州仪器 - TI /
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21页 435K
描述
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH

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GT2034 数据手册

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SN74GTLP2034  
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER  
WITH SPLIT LVTTL PORT AND FEEDBACK PATH  
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001  
DGG OR DGV PACKAGE  
Member of the Texas Instruments  
Widebus Family  
(TOP VIEW)  
TI-OPC Circuitry Limits Ringing on  
Unevenly Loaded Backplanes  
IMODE1  
AI1  
IMODE0  
BIAS V  
B1  
GND  
OEAB  
B2  
ERC  
OEAB  
B3  
1
2
3
4
5
6
7
8
9
48  
47  
46  
45  
44  
43  
42  
41  
40  
CC  
OEC Circuitry Improves Signal Integrity  
and Reduces Electromagnetic Interference  
AO1  
GND  
AI2  
Bidirectional Interface Between GTLP  
Signal Levels and LVTTL Logic Levels  
AO2  
V
Split LVTTL Port Provides a Feedback Path  
for Control and Diagnostics Monitoring  
CC  
AI3  
AO3  
LVTTL Interfaces Are 5-V Tolerant  
GND 10  
AI4  
39 GND  
High-Drive GTLP Open-Drain Outputs  
(100 mA)  
CLKAB/LEAB  
B4  
11  
12  
38  
37  
AO4  
LVTTL Outputs (–24 mA/24 mA)  
AO5 13  
AI5 14  
36 B5  
Variable Edge-Rate Control (ERC) Input  
Selects GTLP Rise and Fall Times for  
Optimal Data-Transfer Rate and Signal  
Integrity in Distributed Loads  
35 CLKBA/LEBA  
34 GND  
GND 15  
AO6 16  
AI6 17  
33 B6  
32 OEBA  
V
18  
31  
V
I
, Power-Up 3-State, and BIAS V  
CC  
CC  
CC  
off  
AO7 19  
30 B7  
Support Live Insertion  
AI7 20  
29 LOOPBACK  
28 GND  
27 B8  
Distributed V and GND Pins Minimize  
High-Speed Switching Noise  
CC  
GND 21  
AO8 22  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
AI8 23  
26  
V
REF  
OMODE0 24  
25 OMODE1  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
description  
The SN74GTLP2034 is a high-drive, 8-bit, three-wire registered transceiver that provides true LVTTL-to-GTLP  
and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and flip-flop modes of  
data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback path for control and  
diagnostics monitoring, the same functionality as the SN74FB2033, but with true logic. The device provides a  
high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal  
levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result  
of GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC  
circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have  
been designed and tested using several backplane models. The high drive allows incident-wave switching in  
heavily loaded backplanes with equivalent load impedance down to 11 Ω.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

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