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GS88237AB-200T PDF预览

GS88237AB-200T

更新时间： 2024-11-11 13:08:07
品牌 Logo 应用领域
GSI 存储静态存储器
页数 文件大小 规格书
28页 722K
描述
Cache SRAM, 256KX36, 2.5ns, CMOS, PBGA119, PLASTIC, BGA-119

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GS88237AB-200T 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA, BGA119,7X17,50针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.74
最长访问时间：2.5 ns其他特性：PIPELINED ARCHITECTURE; IT CAN ALSO OPERATE WITH 3.3V SUPPLY
最大时钟频率 (fCLK)：200 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
长度：22 mm内存密度：9437184 bit
内存集成电路类型：CACHE SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：119字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：1.99 mm
最大待机电流：0.02 A最小待机电流：2.3 V
子类别：SRAMs最大压摆率：0.24 mA
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

GS88237AB-200T 数据手册

 浏览型号GS88237AB-200T的Datasheet PDF文件第2页浏览型号GS88237AB-200T的Datasheet PDF文件第3页浏览型号GS88237AB-200T的Datasheet PDF文件第4页浏览型号GS88237AB-200T的Datasheet PDF文件第5页浏览型号GS88237AB-200T的Datasheet PDF文件第6页浏览型号GS88237AB-200T的Datasheet PDF文件第7页 
GS88237AB-250/225/200/166/150/133  
250 MHz–133 MHz  
119-Bump BGA  
Commercial Temp  
Industrial Temp  
256K x 36  
9Mb Synchronous Burst SRAMs  
2.5 V or 3.3 V V  
DD  
2.5 V or 3.3 V I/O  
SCD and DCD Pipelined Reads  
Features  
The GS88237AB is a SCD (Single Cycle Deselect) and DCD  
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD  
SRAMs pipeline disable commands to the same degree as read  
commands. SCD SRAMs pipeline deselect commands one stage  
less than read commands. SCD RAMs begin turning off their  
outputs immediately after the deselect command has been  
captured in the input registers. DCD RAMs hold the deselect  
command for one full cycle and then begin turning off their  
outputs just after the second rising edge of clock. The user may  
configure this SRAM for either mode of operation using the SCD  
mode input.  
• Single/Dual Cycle Deselect selectable  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• ZQ mode pin for user-selectable high/low output drive  
• 2.5 V or 3.3 V +10%/–10% core power supply  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 119-bump BGA package  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
Functional Description  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write control  
inputs.  
Applications  
The GS88237AB is a 9,437,184-bit high performance  
synchronous SRAM with a 2-bit burst address counter. Although  
of a type originally developed for Level 2 Cache applications  
supporting high performance CPUs, the device now finds  
application in synchronous SRAM applications, ranging from  
DSP main store to networking chip set support.  
FLXDrive™  
The ZQ pin allows selection between high drive strength (ZQ low)  
for multi-drop bus applications and normal drive strength (ZQ  
floating or high) point-to-point applications. See the Output Driver  
Characteristics chart for details.  
Controls  
Addresses, data I/Os, chip enable (E1), address burst control  
Sleep Mode  
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,  
GW) are synchronous and are controlled by a positive-edge-  
triggered clock input (CK). Output enable (G) and power down  
control (ZZ) are asynchronous inputs. Burst cycles can be initiated  
with either ADSP or ADSC inputs. In Burst mode, subsequent  
burst addresses are generated internally and are controlled by  
ADV. The burst address counter may be configured to count in  
either linear or interleave order with the Linear Burst Order (LBO)  
input. The Burst function need not be used. New addresses can be  
loaded on every cycle with no degradation of chip performance.  
Low power (Sleep mode) is attained through the assertion (High)  
of the ZZ signal, or by stopping the clock (CK). Memory data is  
retained during Sleep mode.  
Core and Interface Voltages  
The GS88237AB operates on a 2.5 V or 3.3 V power supply. All  
input are 3.3 V and 2.5 V compatible. Separate output power  
(VDDQ) pins are used to decouple output noise from the internal  
circuits and are 3.3 V and 2.5 V compatible.  
Parameter Synopsis  
-250 -225 -200 -166 -150 -133 Unit  
Pipeline  
3-1-1-1  
t
2.0 2.2 2.5 2.9 3.3 3.5 ns  
4.0 4.4 5.0 6.0 6.7 7.5 ns  
KQ  
tCycle  
3.3 V  
2.5 V  
Current 330 300 270 230 215 190 mA  
Current 320 295 265 225 210 185 mA  
Rev: 1.02 11/2004  
1/28  
© 2002, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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与GS88237AB-200T相关器件

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GS88237AB-225 GSI

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 		256K x 36 9Mb Synchronous Burst SRAMs
GS88237AB-225I GSI

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 		256K x 36 9Mb Synchronous Burst SRAMs
GS88237AB-225IT GSI

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 		Cache SRAM, 256KX36, 2.2ns, CMOS, PBGA119, PLASTIC, BGA-119
GS88237AB-225T GSI

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 		Cache SRAM, 256KX36, 2.2ns, CMOS, PBGA119, PLASTIC, BGA-119
GS88237AB-250 GSI

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 		256K x 36 9Mb Synchronous Burst SRAMs
GS88237AB-250I GSI

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 		256K x 36 9Mb Synchronous Burst SRAMs
GS88237AB-250IT GSI

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 		Cache SRAM, 256KX36, 2ns, CMOS, PBGA119, PLASTIC, BGA-119
GS88237AB-250T GSI

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 		Cache SRAM, 256KX36, 2ns, CMOS, PBGA119, PLASTIC, BGA-119
GS88237AGB-133I GSI

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 		Cache SRAM, 256KX36, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119
GS88237AGB-166I GSI

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 		Cache SRAM, 256KX36, 2.9ns, CMOS, PBGA119, PLASTIC, BGA-119

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