Datasheet > 存储 > SRAM> GS881E18BD-150IV

GS881E18BD-150IV

更新时间： 2024-11-11 03:11:19

品牌	Logo	应用领域
GSI		存储静态存储器
页数	文件大小	规格书
36页	1524K
描述
512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

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GS881E18BD-150IV 数据手册

GS881E18/32/36B(T/D)-xxxV

250 MHz–150 MHz

100-Pin TQFP & 165-bump BGA

Commercial Temp

Industrial Temp

512K x 18, 256K x 32, 256K x 36

9Mb Sync Burst SRAMs

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Linear Burst Order (LBO) input. The Burst function need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Dual Cycle Deselect (DCD) operation

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V or 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP and 165-bump BGA

packages

• RoHS-compliant 100-lead TQFP and 165-bump BGA

packages available

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

DCD Pipelined Reads

The GS881E18/32/36B(T/D)-xxxV is a DCD (Dual Cycle

Deselect) pipelined synchronous SRAM. SCD (Single Cycle

Deselect) versions are also available. DCD SRAMs pipeline

disable commands to the same degree as read commands. DCD

RAMs hold the deselect command for one full cycle and then

begin turning off their outputs just after the second rising edge

of clock.

Functional Description

Byte Write and Global Write

Applications

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

The GS881E18/32/36B(T/D)-xxxV is a 9,437,184-bit high

performance synchronous SRAM with a 2-bit burst address

counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the

device now finds application in synchronous SRAM

applications, ranging from DSP main store to networking chip

set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV) and write control inputs (Bx,

BW, GW) are synchronous and are controlled by a positive-

edge-triggered clock input (CK). Output enable (G) and power

down control (ZZ) are asynchronous inputs. Burst cycles can

be initiated with either ADSP or ADSC inputs. In Burst mode,

subsequent burst addresses are generated internally and are

controlled by ADV. The burst address counter may be

configured to count in either linear or interleave order with the

Core and Interface Voltages

The GS881E18/32/36B(T/D)-xxxV operates on a 1.8 V or 2.5

V power supply. All input are 2.5 V and 1.8 V compatible.

Separate output power (V

) pins are used to decouple

DDQ

output noise from the internal circuits and are 2.5 V and 1.8 V

compatible.

Paramter Synopsis

-250

-200

-150

Unit

t_KQ

3.0

4.0

3.0

5.0

3.8

6.7

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

200

230

170

195

140

160

t_KQ

5.5

6.5

7.5

tCycle

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

160

185

140

160

128

145

Rev: 1.00 6/2006

1/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...36

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与GS881E18BD-150IV相关器件

型号	品牌	获取价格	描述	数据表
GS881E18BD-150IVT	GSI	获取价格	Cache SRAM, 512KX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165
GS881E18BD-150T	GSI	获取价格	Cache SRAM, 512KX18, 7.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165
GS881E18BD-150V	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS881E18BD-166	GSI	获取价格	Cache SRAM, 512KX18, 7ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS881E18BD-166I	GSI	获取价格	Cache SRAM, 512KX18, 7ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS881E18BD-166IT	GSI	获取价格	Cache SRAM, 512KX18, 7ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
GS881E18BD-200	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS881E18BD-200I	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
GS881E18BD-200IT	GSI	获取价格	Cache SRAM, 512KX18, 6.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FPBGA-165
GS881E18BD-200IV	GSI	获取价格	512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

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