Datasheet > GS88118AT-133T

GS88118AT-133T

更新时间： 2024-11-26 18:43:59

品牌	Logo	应用领域
GSI		静态存储器内存集成电路
页数	文件大小	规格书
36页	915K
描述
Cache SRAM, 512KX18, 8.5ns, CMOS, PQFP100, TQFP-100

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技术参数
数据手册

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GS88118AT-133T 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP,
针数：	100	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.B	HTS代码：	8542.32.00.41
风险等级：	5.72	最长访问时间：	8.5 ns
其他特性：	FLOW-THROUGH OR PIPELINED ARCHITECTURE; ALSO OPERATES WITH 3.3V SUPPLY	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	内存密度：	9437184 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	512KX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	2.7 V
最小供电电压 (Vsup)：	2.3 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

GS88118AT-133T 数据手册

GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)

250 MHz–133 MHz

100-Pin TQFP & 165-Bump BGA

Commercial Temp

512K x 18, 256K x 36

2.5 V or 3.3 V V

9Mb Synchronous Burst SRAMs

Industrial Temp

2.5 V or 3.3 V I/O

Flow Through/Pipeline Reads

Features

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

SCD Pipelined Reads

• Automatic power-down for portable applications

• JEDEC-standard packages

The GS88118/36AT/D is a SCD (Single Cycle Deselect)

pipelined synchronous SRAM. DCD (Dual Cycle Deselect)

versions are also available. SCD SRAMs pipeline deselect

commands one stage less than read commands. SCD RAMs

begin turning off their outputs immediately after the deselect

command has been captured in the input registers.

Functional Description

Applications

The GS88118/36AT/D is a 9,437,184-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Controls

Sleep Mode

Addresses, data I/Os, chip enable (E1, E2), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88118/36AT/D operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-250 -225 -200 -166 -150 -133 Unit

Pipeline

3-1-1-1

2.5 2.7 3.0 3.4 3.8 4.0 ns

4.0 4.4 5.0 6.0 6.7 7.5 ns

tCycle

Curr (x18) 280 255 230 200 185 165 mA

Curr (x36) 330 300 270 230 215 190 mA

Flow

Through

2-1-1-1

5.5 6.0 6.5 7.0 7.5 8.5 ns

tCycle

Curr (x18) 175 165 160 150 145 135 mA

Curr (x36) 200 190 180 170 165 150 mA

Rev: 1.04 3/2005

1/36

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...36

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与GS88118AT-133T相关器件

型号	品牌	获取价格	描述	数据表
GS88118AT-150	GSI	获取价格	512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS88118AT-150I	GSI	获取价格	512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS88118AT-150IT	GSI	获取价格	Cache SRAM, 512KX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS88118AT-150T	GSI	获取价格	Cache SRAM, 512KX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS88118AT-166	GSI	获取价格	512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS88118AT-166I	GSI	获取价格	512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS88118AT-166IT	GSI	获取价格	Cache SRAM, 512KX18, 7ns, CMOS, PQFP100, TQFP-100
GS88118AT-200	GSI	获取价格	512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS88118AT-200I	GSI	获取价格	512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS88118AT-200IT	GSI	获取价格	Cache SRAM, 512KX18, 6.5ns, CMOS, PQFP100, TQFP-100

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