Datasheet > 存储 > SRAM> GS880ZV18BGT-300I

GS880ZV18BGT-300I

更新时间： 2024-11-25 02:53:07

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
23页	575K
描述
9Mb Pipelined and Flow Through Synchronous NBT SRAM

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GS880ZV18/36BT-333/300/250/200

100-Pin TQFP

Commercial Temp

Industrial Temp

333 MHz–200 MHz

9Mb Pipelined and Flow Through

Synchronous NBT SRAM

1.8 V V

1.8 V I/O

rail for proper operation. Asynchronous inputs include the

Features

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

• NBT (No Bus Turn Around) functionality allows zero wait

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

• 1.8 V +10%/–10% core power supply

• 1.8 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 2M, 4M, and 18M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

• Pb-Free 100-lead TQFP package available

The GS880ZV18/36BT may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, meaning that in addition to the

rising edge triggered registers that capture input signals, the

device incorporates a rising-edge-triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

Functional Description

The GS880ZV18/36BT is a 9Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

The GS880ZV18/36BT is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

Standard 100-pin TQFP package.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

Paramter Synopsis

-333

-300

-250

-200

Unit

t_KQ

2.5

3.0

2.5

3.3

2.5

4.0

3.0

5.0

tCycle

Pipeline

3-1-1-1

Curr (x18)

Curr (x32/x36)

245

275

225

250

195

220

165

185

t_KQ

4.5

5.0

5.5

6.5

tCycle

Flow Through

2-1-1-1

Curr (x18)

Curr (x32/x36)

195

220

180

200

155

175

140

155

Rev: 1.02 3/2005

1/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...23

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与GS880ZV18BGT-300I相关器件

型号	品牌	获取价格	描述	数据表
GS880ZV18BGT-300IT	GSI	获取价格	ZBT SRAM, 512KX18, 5ns, CMOS, PQFP100, LEAD FREE, TQFP-100
GS880ZV18BGT-333	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880ZV18BGT-333I	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880ZV18BGT-333T	GSI	获取价格	ZBT SRAM, 512KX18, 4.5ns, CMOS, PQFP100, LEAD FREE, TQFP-100
GS880ZV18BT	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880ZV18BT-150	GSI	获取价格	ZBT SRAM, 512KX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS880ZV18BT-150IT	GSI	获取价格	ZBT SRAM, 512KX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS880ZV18BT-200	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880ZV18BT-200I	GSI	获取价格	9Mb Pipelined and Flow Through Synchronous NBT SRAM
GS880ZV18BT-200IT	GSI	获取价格	暂无描述

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