Datasheet > GS88037CGT-333V

GS88037CGT-333V

更新时间： 2024-09-21 13:48:11

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
17页	276K
描述
100 TQFP

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GS88037CGT-333V 数据手册

GS88037CT-xxxV

250 MHz–200 MHz

256K x 36

9Mb Sync Burst SRAM

100-Pin TQFP

Commercial Temp

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Burst mode, subsequent burst addresses are generated

Features

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

• Single Cycle Deselect (SCD) operation

• 1.8 V or 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

SCD Pipelined Reads

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

The GS88037CT-xxxV is a SCD (Single Cycle Deselect)

pipelined synchronous SRAM. DCD (Dual Cycle Deselect)

versions are also available. SCD SRAMs pipeline deselect

commands one stage less than read commands. SCD RAMs

begin turning off their outputs immediately after the deselect

command has been captured in the input registers.

Functional Description

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Applications

The GS88037CT-xxxV is a 9,437,184-bit (8,388,608-bit for

x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Core and Interface Voltages

The GS88037CT-xxxV operates on a 1.8 V or 2.5 V power

supply. All input are 2.5 V and 1.8 V compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuits and are 2.5 V and 1.8 V compatible.

Parameter Synopsis

-250

-200

Unit

Pipeline

3-1-1-1

2.3

4.0

2.7

5.0

tCycle

Curr (x36)

225

195

Rev: 1.04 6/2012

1/17

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...17

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与GS88037CGT-333V相关器件

型号	品牌	获取价格	描述	数据表
GS88037CT-200T	GSI	获取价格	Cache SRAM, 256KX36, 2.7ns, CMOS, PQFP100, TQFP-100
GS88037CT-250IVT	GSI	获取价格	Cache SRAM, 256KX36, 2.5ns, CMOS, PQFP100, TQFP-100
GS88037CT-300	GSI	获取价格	Cache SRAM, 256KX36, 2.2ns, CMOS, PQFP100, TQFP-100
GS88037CT-300IT	GSI	获取价格	Cache SRAM, 256KX36, 2.2ns, CMOS, PQFP100, TQFP-100
GS88037CT-300T	GSI	获取价格	Cache SRAM, 256KX36, 2.2ns, CMOS, PQFP100, TQFP-100
GS880E18AGT-133	GSI	获取价格	Cache SRAM, 512KX18, 8.5ns, CMOS, PQFP100, TQFP-100
GS880E18AGT-133I	GSI	获取价格	Cache SRAM, 512KX18, 8.5ns, CMOS, PQFP100, TQFP-100
GS880E18AGT-133T	GSI	获取价格	Cache SRAM, 512KX18, 8.5ns, CMOS, PQFP100, TQFP-100
GS880E18AGT-150I	GSI	获取价格	Cache SRAM, 512KX18, 7.5ns, CMOS, PQFP100, TQFP-100
GS880E18AGT-150IT	GSI	获取价格	Cache SRAM, 512KX18, 7.5ns, CMOS, PQFP100, TQFP-100

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