Datasheet > GS88037CGT-300I

GS88037CGT-300I

更新时间： 2024-11-09 14:57:11

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
19页	300K
描述
100 TQFP

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数据手册

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GS88037CGT-300I 数据手册

GS88037CT-xxxI

333 MHz–200 MHz

256K x 36

9Mb Sync Burst SRAM

100-Pin TQFP

Industrial Temp

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Burst mode, subsequent burst addresses are generated

Features

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

SCD Pipelined Reads

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• Ro-HS-compliant 100-lead TQFP package available

The GS88037CT is a SCD (Single Cycle Deselect) pipelined

synchronous SRAM. DCD (Dual Cycle Deselect) versions are

also available. SCD SRAMs pipeline deselect commands one

stage less than read commands. SCD RAMs begin turning off

their outputs immediately after the deselect command has been

captured in the input registers.

Functional Description

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Applications

The GS88037CT is a 9,437,184-bit (8,388,608-bit for x32

version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Core and Interface Voltages

The GS88037CT operates on a 2.5 V or 3.3 V power supply.

All input are 3.3 V and 2.5 V compatible. Separate output

power (V

) pins are used to decouple output noise from the

DDQ

internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-333I

-300I

-250I

-200I

Unit

Pipeline

3-1-1-1

2.0

3.0

2.2

3.3

2.3

4.0

2.7

5.0

tCycle

Curr (x36)

300

280

245

215

Rev: 1.04 7/2012

1/19

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...19

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与GS88037CGT-300I相关器件

型号	品牌	获取价格	描述	数据表
GS88037CGT-300IV	GSI	获取价格	100 TQFP
GS88037CGT-300V	GSI	获取价格	100 TQFP
GS88037CGT-333	GSI	获取价格	100 TQFP
GS88037CGT-333I	GSI	获取价格	100 TQFP
GS88037CGT-333IV	GSI	获取价格	100 TQFP
GS88037CGT-333V	GSI	获取价格	100 TQFP
GS88037CT-200T	GSI	获取价格	Cache SRAM, 256KX36, 2.7ns, CMOS, PQFP100, TQFP-100
GS88037CT-250IVT	GSI	获取价格	Cache SRAM, 256KX36, 2.5ns, CMOS, PQFP100, TQFP-100
GS88037CT-300	GSI	获取价格	Cache SRAM, 256KX36, 2.2ns, CMOS, PQFP100, TQFP-100
GS88037CT-300IT	GSI	获取价格	Cache SRAM, 256KX36, 2.2ns, CMOS, PQFP100, TQFP-100

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