GS8673ET18/36BK-675/625/550/500
675 MHz–500 MHz
1.35 V VDD
1.2 V to 1.5 V VDDQ
260-Ball BGA
Commercial Temp
Industrial Temp
72Mb SigmaDDR-IIIe™
Burst of 2 ECCRAM™
Features
Clocking and Addressing Schemes
• On-Chip ECC with virtually zero SER
• Configurable Read Latency (3.0 or 2.0 cycles)
• Simultaneous Read and Write SigmaDDR-IIIe™ Interface
• Common I/O Bus
• Double Data Rate interface
• Burst of 2 Read and Write
The GS8673ET18/36BK SigmaDDR-IIIe ECCRAMs are
synchronous devices. They employ dual, single-ended master
clocks, CK and CK. These clocks are single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. CK and CK are used to control the address and control
input registers, as well as all output timing.
• Pipelined read operation
• Fully coherent Read and Write pipelines
• 1.35 V nominal VDD
The KD and KD clocks are dual mesochronous (with respect to
CK and CK) input clocks that are used solely to control the
data input registers. Consequently, data input setup and hold
windows can be optimized independently of address and
control input setup and hold windows.
• 1.2 V JESD8-16A BIC-3 Compliant Interface
• 1.5 V HSTL Interface
• ZQ pin for programmable output drive impedance
• ZT for programmable input termination impedance
• Configurable Input Termination
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package
–K: 5/6 RoHS-compliant package
Each internal read and write operation in a SigmaDDR-IIIe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaDDR-IIIe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 4M x 18 has
2M addressable index).
SigmaDDR-IIIe™ Family Overview
The SigmaDDR-IIIe family of SRAMs are the Common I/O
half of the SigmaQuad-IIIe/SigmaDDR-IIIe family of high
performance SRAMs. Although very similar to GSI's second
generation of networking SRAMs, the SigmaQuad-II/
SigmaDDR-II family, this third generation family of SRAMs
offers new features that allow much higher speeds, such as
user-configurable on-die input termination, improved output
signal integrity, and adjustable pipeline length.
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles, etc. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
Parameter Synopsis
VDD
Speed Bin
Operating Frequency
Data Rate (per pin)
Read Latency
-675
-625
-550
-500
675 / 450 MHz
625 / 400 MHz
550 / 375 MHz
500 / 333 MHz
1350 / 900 Mbps
1250 / 800 Mbps
1100 / 750 Mbps
1000 / 666 Mbps
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
1.3V to 1.4V
1.3V to 1.4V
1.25V to 1.4V
1.25V to 1.4V
Rev: 1.06 12/2017
1/37
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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