Datasheet > GS8662TT20CGD-550I

GS8662TT20CGD-550I

更新时间： 2023-12-06 20:13:34

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165 BGA

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GS8662TT20CGD-550I 数据手册

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GS8662TT20/38CGD-633/550/500

633 MHz–500 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaDDR-II+

Burst of 2 SRAM

1.8 V V

1.8 V or 1.5 V I/O

Features

Clocking and Addressing Schemes

• 2.5 Clock Latency

The GS8662TT20/38CGD SigmaDDR-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

• Simultaneous Read and Write SigmaDDR^TMInterface

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

Each internal read and write operation in a SigmaDDR-II+ B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore, the address field of a

SigmaDDR-II+ B2 RAM is always one address pin less than

the advertised index depth (e.g., the 4M x 18 has a 2M

addressable index).

• Dual-Range On-Die Termination (ODT) on Data (D), Byte

Write (BW), and Clock (K, K) inputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• RoHS-compliant 165-bump BGA package

SigmaDDR-II™ Family Overview

The GS8662TT20/38CGD are built in compliance with the

SigmaDDR-II+ SRAM pinout standard for Common I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662TT20/38CGD SigmaDDR-II+ SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Parameter Synopsis

-633

-550

-500

2.0 ns

0.45 ns

tKHKH

tKHQV

1.58 ns

0.45 ns

1.81 ns

0.45 ns

Rev: 1.01 9/2019

1/24

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...24

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