Datasheet > GS8662T20BD-550I

GS8662T20BD-550I

更新时间： 2024-11-10 14:57:07

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
31页	535K
描述
165 BGA

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GS8662T20BD-550I 数据手册

GS8662T20/38BD-550/500/450/400/350

GS8662T06/11BD-500/450/400/350

550 MHz–350 MHz

72Mb SigmaDDR^TM-II+

Burst of 2 SRAM

165-Bump BGA

Commercial Temp

Industrial Temp

1.8 V V

1.8 V or 1.5 V I/O

SRAMs are just one element in a family of low power, low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

Features

• 2.5 Clock Latency

• Simultaneous Read and Write SigmaDDR Interface

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) inputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

Clocking and Addressing Schemes

The GS8662T06/11/20/38BD SigmaDDR-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

• Pipelined read operation

Each internal read and write operation in a SigmaDDR-II+ B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore, the address field of a

SigmaDDR-II+ B2 RAM is always one address pin less than

the advertised index depth (e.g., the 8M x 8 has an 4M

addressable index).

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

SigmaDDR-II™ Family Overview

The GS8662T06/11/20/38BD are built in compliance with the

SigmaDDR-II+ SRAM pinout standard for Common I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662T06/11/20/38BD SigmaDDR-II+

Parameter Synopsis (x18/x36)

-550

-500

2.0 ns

0.33 ns

-450

2.2 ns

0.37 ns

-400

2.5 ns

0.45 ns

-350

tKHKH

tKHQV

1.81 ns

0.29ns

2.86 ns

0.45 ns

Parameter Synopsis (x8/x9)

-500

-450

2.2 ns

0.37ns

-400

-350

tKHKH

tKHQV

2.0 ns

2.5 ns

2.86 ns

0.45 ns

0.33 ns

0.45 ns

Rev: 1.02c 8/2017

1/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...31

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与GS8662T20BD-550I相关器件

型号	品牌	获取价格	描述	数据表
GS8662T20BGD-350	GSI	获取价格	165 BGA
GS8662T20BGD-350I	GSI	获取价格	165 BGA
GS8662T20BGD-400	GSI	获取价格	165 BGA
GS8662T20BGD-400I	GSI	获取价格	165 BGA
GS8662T20BGD-450	GSI	获取价格	165 BGA
GS8662T20BGD-450I	GSI	获取价格	165 BGA
GS8662T20BGD-500	GSI	获取价格	165 BGA
GS8662T20BGD-500I	GSI	获取价格	165 BGA
GS8662T20BGD-550	GSI	获取价格	165 BGA
GS8662T20BGD-550I	GSI	获取价格	165 BGA

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