Datasheet > GS8662S09BGD-333I

GS8662S09BGD-333I

更新时间： 2024-11-06 13:48:11

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
35页	1285K
描述
165 BGA

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GS8662S08/09/18/36BD-400/350/333/300/250

72Mb SigmaSIO^TMDDR -II

Burst of 2 SRAM

400 MHz–250 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

1.8 V V

1.8 V and 1.5 V I/O

Features

Clocking and Addressing Schemes

• Simultaneous Read and Write SigmaSIO™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• DLL circuitry for wide output data valid window and future

frequency scaling

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous

device. It employs dual input register clock inputs, K and K.

The device also allows the user to manipulate the output

K clocks are routed internally to fire the output registers

instead. Each Burst of 2 SigmaSIO DDR-II SRAM also

supplies Echo Clock outputs, CQ and CQ, which are

synchronized with read data output. When used in a source

synchronous clocking scheme, the Echo Clock outputs can be

used to fire input registers at the data’s destination.

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

Each internal read and write operation in a SigmaSIO DDR-II

B2 RAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaSIO DDR-II B2 is always one address pin less

than the advertised index depth (e.g., the 8M x 8 has an 4M

addressable index).

SigmaSIO™ Family Overview

GS8662S08/09/18/36BD are built in compliance with the

SigmaSIO DDR-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. These are the first in a family of wide, very low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

Parameter Synopsis

-400

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

tKHKH

tKHQV

Rev: 1.02c 12/2011

1/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...35

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与GS8662S09BGD-333I相关器件

型号	品牌	获取价格	描述	数据表
GS8662S09BGD-333IT	GSI	获取价格	Standard SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216
GS8662S09BGD-333T	GSI	获取价格	Standard SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, MO-216
GS8662S09BGD-400	GSI	获取价格	165 BGA
GS8662S09BGD-400I	GSI	获取价格	165 BGA
GS8662S09E-167	GSI	获取价格	72Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8662S09E-167I	GSI	获取价格	72Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8662S09E-167T	GSI	获取价格	DDR SRAM, 8MX9, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-165
GS8662S09E-200	GSI	获取价格	72Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8662S09E-200I	GSI	获取价格	72Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8662S09E-250	GSI	获取价格	72Mb Burst of 2 DDR SigmaSIO-II SRAM

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