Datasheet > GS8662DT19RE-250M

GS8662DT19RE-250M

更新时间： 2023-12-06 20:13:34

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
28页	728K
描述
165 BGA

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GS82582DT19/37RE-350M/250M

GS81302DT19/37RE-350M/250M

GS8662DT19/37RE-350M/250M

350 MHz–250 MHz

Rad-Tolerant SRAM

288Mb/144Mb/72Mb Burst of 4 SigmaQuad-II+

165-Bump BGA

Military Temp

1.8 V V

1.8 V and 1.5 V I/O

Features

SigmaQuad™ Family Overview

• Aerospace-Level Product

The GS82582DT19/37, GS81302DT19/37, and

• 2.0 clock Latency

GS8662DT19/37 are built in compliance with the SigmaQuad-

II+ SRAM pinout standard for Separate I/O synchronous

SRAMs. They are 301,989,888-bit (288Mb), 150,994,944-bit

(144Mb), and 75,497,472-bit (72Mb) SRAMs. These

SigmaQuad SRAMs comprise a family of low power, low

voltage HSTL I/O Radiation-Tolerant (Rad-Tolerant) SRAMs

designed to operate in Radiation environments.

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• Dual-Range On-Die Termination (ODT) on Data (D), Byte

Write (BW), and Clock (K, K) inputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

Clocking and Addressing Schemes

The Rad-Tolerant SigmaQuad-II+ SRAMs are synchronous

devices. They employ two input register clock inputs, K and K.

K and K are independent single-ended clock inputs, not

differential inputs to a single differential clock input buffer.

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump leaded BGA package

Each internal read and write operation in a SigmaQuad-II+ B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaQuad-II+ B4 RAM is always two address pins

less than the advertised index depth (e.g., the 16M x 18 has a

4M addressable index).

Radiation Performance

• Total Ionizing Dose (TID) > 50krads(Si)

• Destructive Single Event Latchup Immunity >42.2 MeV.cm²/mg

(100C)

Parameter Synopsis

-350M

2.86 ns

0.45 ns

-250M

4.0 ns

tKHKH

tKHQV

0.45 ns

Rev: 1.01 3/2021

1/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...28

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与GS8662DT19RE-250M相关器件

型号	品牌	获取价格	描述	数据表
GS8662DT19RE-350M	GSI	获取价格	165 BGA
GS8662DT20	GSI	获取价格	72Mb SigmaQuad-IITM Burst of 4 SRAM
GS8662DT20BD-350	GSI	获取价格	165 BGA
GS8662DT20BD-350I	GSI	获取价格	JEDEC-standard pinout and package
GS8662DT20BD-400	GSI	获取价格	165 BGA
GS8662DT20BD-400I	GSI	获取价格	165 BGA
GS8662DT20BD-450	GSI	获取价格	165 BGA
GS8662DT20BD-450I	GSI	获取价格	JEDEC-standard pinout and package
GS8662DT20BD-500	GSI	获取价格	Dual Double Data Rate interface
GS8662DT20BD-500I	GSI	获取价格	165 BGA

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