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GS8644V18B-200 PDF预览

GS8644V18B-200

更新时间： 2024-11-19 05:10:51
品牌 Logo 应用领域
GSI 存储内存集成电路静态存储器
页数 文件大小 规格书
40页 1155K
描述
4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs

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GS8644V18B-200 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA,针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.92
Is Samacsys：N最长访问时间：6.5 ns
其他特性：PIPELINED OR FLOW-THROUGH ARCHITECTUREJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：75497472 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：119
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4MX18
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.99 mm
最大供电电压 (Vsup)：2 V最小供电电压 (Vsup)：1.6 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

GS8644V18B-200 数据手册

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Product Preview  
GS8644V18(B/E)/GS8644V36(B/E)/GS8644V72(C)  
250 MHz–133MHz  
119-, 165-, & 209-Pin BGA  
Commercial Temp  
Industrial Temp  
4M x 18, 2M x 36, 1M x 72  
72Mb S/DCD Sync Burst SRAMs  
1.8 V V  
DD  
1.8 V I/O  
Data Output Register. Holding FT high places the RAM in  
Pipeline mode, activating the rising-edge-triggered Data Output  
Register.  
Features  
• FT pin for user-configurable flow through or pipeline operation  
• Single/Dual Cycle Deselect selectable  
• IEEE 1149.1 JTAG-compatible Boundary Scan  
• ZQ mode pin for user-selectable high/low output drive  
• 1.8 V +10%/–10% core power supply and I/O  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to SCD x18/x36 Interleaved Pipeline mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
SCD and DCD Pipelined Reads  
The GS8644V18/36/72 is a SCD (Single Cycle Deselect) and  
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD  
SRAMs pipeline disable commands to the same degree as read  
commands. SCD SRAMs pipeline deselect commands one stage  
less than read commands. SCD RAMs begin turning off their  
outputs immediately after the deselect command has been  
captured in the input registers. DCD RAMs hold the deselect  
command for one full cycle and then begin turning off their  
outputs just after the second rising edge of clock. The user may  
configure this SRAM for either mode of operation using the SCD  
mode input.  
• Automatic power-down for portable applications  
• JEDEC-standard 119-, 165-, and 209-bump BGA package  
Functional Description  
Applications  
The GS8644V18/36/72 is a 75,497,472-bit high performance  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write control  
inputs.  
synchronous SRAM with a 2-bit burst address counter. Although  
of a type originally developed for Level 2 Cache applications  
supporting high performance CPUs, the device now finds  
application in synchronous SRAM applications, ranging from  
DSP main store to networking chip set support.  
Controls  
FLXDrive™  
Addresses, data I/Os, chip enable (E1), address burst control  
The ZQ pin allows selection between high drive strength (ZQ low)  
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,  
GW) are synchronous and are controlled by a positive-edge-  
triggered clock input (CK). Output enable (G) and power down  
control (ZZ) are asynchronous inputs. Burst cycles can be initiated  
with either ADSP or ADSC inputs. In Burst mode, subsequent  
burst addresses are generated internally and are controlled by  
ADV. The burst address counter may be configured to count in  
either linear or interleave order with the Linear Burst Order (LBO)  
input. The Burst function need not be used. New addresses can be  
loaded on every cycle with no degradation of chip performance.  
for multi-drop bus applications and normal drive strength (ZQ  
floating or high) point-to-point applications. See the Output Driver  
Characteristics chart for details.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion (High)  
of the ZZ signal, or by stopping the clock (CK). Memory data is  
retained during Sleep mode.  
Core and Interface Voltages  
The GS8644V18/36/72 operates on a 2.5 V or 3.3 V power  
supply. All input are 3.3 V and 2.5 V compatible. Separate output  
Flow Through/Pipeline Reads  
power (VDDQ) pins are used to decouple output noise from the  
The function of the Data Output register can be controlled by the  
internal circuits and are 3.3 V and 2.5 V compatible.  
user via the FT mode . Holding the FT mode pin low places the  
RAM in Flow Through mode, causing output data to bypass the  
Parameter Synopsis  
-250 -225 -200 -166 -150 -133 Unit  
t
KQ(x18/x36)  
tKQ(x72)  
tCycle  
2.3  
2.6  
4.0  
2.5  
2.7  
4.4  
2.7  
2.8  
5.0  
2.9  
2.9  
6.0  
3.3  
3.3  
6.7  
3.5  
3.5  
7.5  
ns  
ns  
ns  
Pipeline  
3-1-1-1  
Curr (x18)  
Curr (x36)  
Curr (x72)  
385  
450  
540  
360  
415  
505  
335  
385  
460  
305  
345  
405  
295 265  
325 295  
385 345  
mA  
mA  
mA  
tKQ  
6.5  
6.5  
6.5  
6.5  
6.5  
6.5  
8.0  
8.0  
8.5  
8.5  
8.5  
8.5  
ns  
ns  
tCycle  
Flow  
Through  
2-1-1-1  
Curr (x18)  
Curr (x36)  
Curr (x72)  
265  
290  
345  
265  
290  
345  
265  
290  
345  
255  
280  
335  
240 225  
265 245  
315 300  
mA  
mA  
mA  
Rev: 1.03 11/2004  
1/40  
© 2003, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...40

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