GS8640F18/32/36GT-6.5
6.5 ns
100-Pin TQFP
Commercial Temp
Industrial Temp
4M x 18, 2M x 32, 2M x 36
72Mb Sync Burst SRAMs
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Features
• Flow Through mode operation
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• 6/6 RoHS-compliant 100-lead TQFP package
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Functional Description
Applications
The GS8640F18/32/36GT is a 75,497,472-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8640F18/32/36GT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
Controls
output power (V
) pins are used to decouple output noise
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
DDQ
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-6.5
Unit
tKQ
tCycle
6.5
6.5
ns
ns
Flow Through
2-1-1-1
Curr (x18)
Curr (x32/x36)
245
280
mA
mA
Rev: 1.00 10/2013
1/22
© 2013, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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