GS840F18AGT-10

更新时间： 2024-11-09 04:01:59

品牌	Logo	应用领域
GSI		存储静态存储器
页数	文件大小	规格书
21页	556K
描述
256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs

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技术参数
数据手册

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GS840F18AGT-10 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.82
最长访问时间：	10 ns	其他特性：	FLOW-THROUGH ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e3
长度：	20 mm	内存密度：	4718592 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	PURE MATTE TIN
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

GS840F18AGT-10 数据手册

GS840F18/32/36AT-7.5/8/8.5/10/12

7.5 ns – 12 ns

TQFP

Commercial Temp

Industrial Temp

256K x 18, 128K x 32, 128K x 36

4Mb Sync Burst SRAMs

3.3 V V

3.3 V and 2.5 V I/O

Burst mode, subsequent burst addresses are generated

Features

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

• Flow Through mode operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

Designing For Compatibility

The JEDEC Standard for Burst RAMS calls for a FT mode pin

option (pin 14 on TQFP). Board sites for Flow Through Burst

RAMS should be designed with V connected to the FT pin

location to ensure the broadest access to multiple vendor

sources. Boards designed with FT pin pads tied low may be

stuffed with GSI’s Pipeline/Flow Through-configurable Burst

RAMS or any vendor’s Flow Through or configurable Burst

SRAM. Bumps designed with the FT pin location tied high or

floating must employ a non-configurable Flow Through Burst

RAM, like this RAM, to achieve flow through functionality.

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP

• Pb-Free 100-lead TQFP package available

Functional Description

Applications

The GS840F18/32/36A is a 4,718,592-bit (4,194,304-bit for

x32 version) high performance synchronous SRAM with a 2-

bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support. The

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

GS840F18/32/36A is available in a JEDEC standard 100-lead

TQFP package.

Low power (Sleep mode) is attained through the assertion

(high) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enables (E¹, E2, E3), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Core and Interface Voltages

The GS840F18/32/36A operates on a 3.3 V power supply and

all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

) pins are used to decouple output noise

DDQ

from the internal circuit.

Parameter Synopsis

–7.5

-8

-8.5

-10

-12

Flow

t^KQ

7.5 ns

8 ns

9 ns

8.5 ns

10 ns

12 ns

15 ns

Through tCycle 8.5 ns

2-1-1-1 I^DD

245 mA 210 mA 190 mA 165 mA 135 mA

Rev: 1.09 10/2004

1/21

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...21

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与GS840F18AGT-10相关器件

型号	品牌	获取价格	描述	数据表
GS840F18AGT-10I	GSI	获取价格	256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840F18AGT-10T	GSI	获取价格	暂无描述
GS840F18AGT-12	GSI	获取价格	256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840F18AGT-12I	GSI	获取价格	256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840F18AGT-12IT	GSI	获取价格	Cache SRAM, 256KX18, 12ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS840F18AGT-7.5	GSI	获取价格	256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840F18AGT-7.5I	GSI	获取价格	256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840F18AGT-8	GSI	获取价格	256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840F18AGT-8.5	GSI	获取价格	256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS840F18AGT-8.5I	GSI	获取价格	256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs

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