Datasheet > GS84032AB-180TT

GS84032AB-180TT

更新时间： 2024-11-27 19:51:23

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
29页	733K
描述
SRAM

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技术参数
数据手册

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GS84032AB-180TT 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.92	湿度敏感等级：	3
Base Number Matches：	1

GS84032AB-180TT 数据手册

GS84018/32/36AT/B-190/180/166/150/100

TQFP, BGA

Commercial Temp

Industrial Temp

190 MHz–100 MHz

256K x 18, 128K x 32, 128K x 36

4Mb Sync Burst SRAMs

3.3 V V

3.3 V and 2.5 V I/O

counter may be configured to count in either linear or

Features

interleave order with the Linear Burst Order (LBO) input. The

burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

• FT pin for user-configurable flow through or pipelined

operation

• Single Cycle Deselect (SCD) operation

• 3.3 V +10%/–5% core power supply

Flow Through/Pipeline Reads

• 2.5 V or 3.3 V I/O supply

The function of the Data Output register can be controlled by

the user via the FT mode pin/bump (pin 14 in the TQFP and

bump 5R in the BGA). Holding the FT mode pin/bump low

places the RAM in Flow Through mode, causing output data to

bypass the Data Output Register. Holding FT high places the

RAM in Pipelined mode, activating the rising-edge-triggered

Data Output Register.

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock control, registered, address, data, and control

• Internal self-timed write cycle

SCD Pipelined Reads

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP or 119-Bump BGA package

The GS84018/32/36A is an SCD (Single Cycle Deselect)

pipelined synchronous SRAM. DCD (Dual Cycle Deselect)

versions are also available. SCD SRAMs pipeline deselect

commands one stage less than read commands. SCD RAMs

begin turning off their outputs immediately after the deselect

command has been captured in the input registers.

Functional Description

Applications

The GS84018/32/36A is a 4,718,592-bit (4,194,304-bit for

x32 version) high performance synchronous SRAM with a 2-

bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications ranging from DSP main store

to networking chip set support. The GS84018/32/36A is

available in a JEDEC standard 100-lead TQFP or 119-Bump

BGA package.

Byte Write and Global Write

Byte write operation is performed by using byte write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Controls

Addresses, data I/Os, chip enables (E¹, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

Core and Interface Voltages

The GS84018/32/36A operates on a 3.3 V power supply and

all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

) pins are used to de-couple output noise

DDQ

from the internal circuit.

Parameter Synopsis

–190

–180

–166

–150

–100

tCycle 5.3 ns 5.5 ns 6.0 ns 6.6 ns

10 ns

Pipeline

3-1-1-1

t^KQ

3.0 ns 3.0 ns 3.5 ns 3.8 ns 4.5 ns

370 mA 335 mA 310 mA 280 mA 190 mA

IDD

Flow

t^KQ

7.5 ns

8 ns

9 ns

8.5 ns

10 ns

12 ns

15 ns

Through tCycle 8.5 ns

2-1-1-1 I^DD

245 mA 210 mA 190 mA 165 mA 135 mA

Rev: 1.14a 7/2004

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...29

中文翻译

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与GS84032AB-180TT相关器件

型号	品牌	获取价格	描述	数据表
GS84032AB-190	GSI	获取价格	Cache SRAM, 128KX32, 7.5ns, CMOS, PBGA119, FPBGA-119
GS84032AB-190I	GSI	获取价格	Cache SRAM, 128KX32, 7.5ns, CMOS, PBGA119, FPBGA-119
GS84032AB-190IT	GSI	获取价格	Cache SRAM, 128KX32, 7.5ns, CMOS, PBGA119, FPBGA-119
GS84032AGB-190I	GSI	获取价格	Cache SRAM, 128KX32, 7.5ns, CMOS, PBGA119, ROHS COMPLIANT, FPBGA-119
GS84032AGT-166I	GSI	获取价格	Cache SRAM, 128KX32, 8.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS84032AGT-166IT	GSI	获取价格	Cache SRAM, 128KX32, 8.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS84032AGT-180IT	GSI	获取价格	Cache SRAM, 128KX32, 8ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS84032AGT-190	GSI	获取价格	Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
GS84032AT-100	GSI	获取价格	256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs
GS84032AT-100I	GSI	获取价格	256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs

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