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GS84032AB-180T PDF预览

GS84032AB-180T

更新时间： 2024-11-27 13:08:03
品牌 Logo 应用领域
GSI 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
31页 884K
描述
Cache SRAM, 128KX32, 8ns, CMOS, PBGA119, FPBGA-119

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GS84032AB-180T 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA, BGA153,9X17,50针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.72
Is Samacsys：N最长访问时间：8 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：180 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：4194304 bit内存集成电路类型：CACHE SRAM
内存宽度：32湿度敏感等级：3
功能数量：1端子数量：119
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX32
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA153,9X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：2.19 mm最大待机电流：0.02 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.335 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GS84032AB-180T 数据手册

 浏览型号GS84032AB-180T的Datasheet PDF文件第2页浏览型号GS84032AB-180T的Datasheet PDF文件第3页浏览型号GS84032AB-180T的Datasheet PDF文件第4页浏览型号GS84032AB-180T的Datasheet PDF文件第5页浏览型号GS84032AB-180T的Datasheet PDF文件第6页浏览型号GS84032AB-180T的Datasheet PDF文件第7页 
Preliminary  
GS84018/32/36AT/B-180/166/150/100  
TQFP, BGA  
Commercial Temp  
Industrial Temp  
180 MHz–100 MHz  
3.3 V VDD  
3.3 V and 2.5 V I/O  
256K x 18, 128K x 32, 128K x 36  
4Mb Sync Burst SRAMs  
counter may be configured to count in either linear or  
Features  
interleave order with the Linear Burst Order (LBO) input. The  
burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
• FT pin for user-configurable flow through or pipelined  
operation  
• Single Cycle Deselect (SCD) operation  
• 3.3 V +10%/–5% core power supply  
Flow Through/Pipeline Reads  
The function of the Data Output register can be controlled by  
the user via the FT mode pin/bump (pin 14 in the TQFP and  
bump 5R in the BGA). Holding the FT mode pin/bump low  
places the RAM in Flow Through mode, causing output data to  
bypass the Data Output Register. Holding FT high places the  
RAM in Pipelined mode, activating the rising-edge-triggered  
Data Output Register.  
• 2.5 V or 3.3 V I/O supply  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Default to Interleaved Pipelined mode  
• Byte Write (BW) and/or Global Write (GW) operation  
• Common data inputs and data outputs  
• Clock control, registered, address, data, and control  
• Internal self-timed write cycle  
SCD Pipelined Reads  
• Automatic power-down for portable applications  
• JEDEC standard 100-lead TQFP or 119-Bump BGA package  
The GS84018/32/36A is an SCD (Single Cycle Deselect)  
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)  
versions are also available. SCD SRAMs pipeline deselect  
commands one stage less than read commands. SCD RAMs  
begin turning off their outputs immediately after the deselect  
command has been captured in the input registers.  
–180  
–166  
–150  
–100  
tCycle  
tKQ  
IDD  
5.5 ns  
3.0 ns  
6.0 ns  
3.5 ns  
6.6 ns  
3.8 ns  
10 ns  
4.5 ns  
105 mA  
Pipeline  
3-1-1-1  
185 mA 170 mA 155 mA  
Byte Write and Global Write  
Flow  
Through tCycle  
2-1-1-1 IDD  
tKQ  
8 ns  
9.1 ns  
8.5 ns  
10 ns  
10 ns  
12 ns  
12 ns  
15 ns  
80 mA  
Byte write operation is performed by using byte write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
115 mA 105 mA 100 mA  
Functional Description  
Sleep Mode  
Applications  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
The GS84018/32/36A is a 4,718,592-bit (4,194,304-bit for  
x32 version) high performance synchronous SRAM with a 2-  
bit burst address counter. Although of a type originally  
developed for Level 2 Cache applications supporting high  
performance CPUs, the device now finds application in  
synchronous SRAM applications ranging from DSP main store  
to networking chip set support. The GS84018/32/36A is  
available in a JEDEC standard 100-lead TQFP or 119-Bump  
BGA package.  
Core and Interface Voltages  
The GS84018/32/36A operates on a 3.3 V power supply and  
all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate  
output power (V  
) pins are used to de-couple output noise  
DDQ  
from the internal circuit.  
Controls  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
Rev: 1.12 7/2002  
1/31  
© 1999, Giga Semiconductor, Inc.  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
1234567...31

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 		256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs

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